Random logic
Unstructured semiconductor logic design
general/instruction-processing
Cycles per instruction
Aspect of CPU performance
general/instruction-processing
Hazard (computer architecture)
Problems with the instruction pipeline in central processing unit (CPU) microarchitectures
general/instruction-processing
Pipeline stall
Delay in the execution of a processor instruction in a pipeline
general/instruction-processing
Instruction cycle
Basic instruction cycle in a computer
general/instruction-processing
Tomasulo's algorithm
Computer architecture hardware algorithm
general/instruction-processing
Control store
general/instruction-processing
Delay slot
Instruction slot being executed without the effects of a preceding instruction
general/instruction-processing
Anticiparallelism
general/instruction-processing
Pipeline (computing)
Data processing chain
general/instruction-processing
Micro-operation
Low-level instructions used in some designs to implement complex machine instructions
general/instruction-processing
Scoreboarding
Instruction scheduling method
general/instruction-processing
Register window
CPU architecture feature to improve performance
general/instruction-processing
Prefetch input queue
CPU optimization unit
general/instruction-processing
Reservation station
general/instruction-processing
Branch predictor
Digital circuit
general/instruction-processing
Instructions per cycle
Average number of instructions executed for each clock cycle
general/instruction-processing
Slipstream (computer science)
general/instruction-processing
Interlock (engineering)
Feature that makes two mechanisms mutually interdependent
general/instruction-processing
Hardware scout
general/instruction-processing
Classic RISC pipeline
Instruction pipeline
general/instruction-processing
Minimal instruction set computer
CPU architecture
general/instruction-processing
Runahead
Microprocessing technique
general/instruction-processing
Microcode
Layer of hardware-level instructions or data structures
general/instruction-processing
Out-of-order execution
Computing paradigm to improve computational efficiency
general/instruction-processing