Cycles per instruction

Definition

The average of Cycles Per Instruction in a given process (CPI) is defined by the following weighted average:

: \mathrm{CPI} := \frac{\Sigma_i(\mathrm{IC}_i)(\mathrm{CC}_i)}{\mathrm{IC}} = \frac{\Sigma_i(\mathrm{IC}_i \cdot \mathrm{CC}_i)}{\Sigma_i(\mathrm{IC}_i)}

Where \mathrm{IC}_i is the number of instructions for a given instruction type i, \mathrm{CC}_i is the clock-cycles for that instruction type and \mathrm{IC}=\Sigma_i(\mathrm{IC}_i) is the total instruction count. The summation sums over all instruction types for a given benchmarking process.

Explanation

Let us assume a classic RISC pipeline, with the following five stages:

1. Instruction fetch cycle (IF).
2. Instruction decode/Register fetch cycle (ID).
3. Execution/Effective address cycle (EX).
4. Memory access (MEM).
5. Write-back cycle (WB).

Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without pipelining, in a multi-cycle processor, a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5, therefore the number of clock cycles it takes to execute an instruction is five (CPI = 5 1). In this case, the processor is said to be subscalar. With pipelining, a new instruction is fetched every clock cycle by exploiting instruction-level parallelism, therefore, since one could theoretically have five instructions in the five pipeline stages at once (one instruction per stage), a different instruction would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1 (CPI = 1). In this case, the processor is said to be scalar.

With a single-execution-unit processor, the best CPI attainable is 1. However, with a multiple-execution-unit processor, one may achieve even better CPI values (CPI

Examples

Example 1

For the multi-cycle MIPS, there are five types of instructions:

• Load (5 cycles)
• Store (4 cycles)
• R-type (4 cycles)
• Branch (3 cycles)
• Jump (3 cycles)

If a program has:

• 50% load instructions
• 25% store instructions
• 15% R-type instructions
• 8% branch instructions
• 2% jump instructions

then, the CPI is:

\text{CPI} = \frac{5 \times 50 + 4 \times 25 + 4 \times 15 + 3 \times 8 + 3 \times 2}{100} = 4.4

Example 2Advanced Computer Architecture by Kai Hwang, Chapter 1, Exercise Problem 1.1

A 400MHz processor was used to execute a benchmark program with the following instruction mix and clock cycle count:

Determine the effective CPI, MIPS (Millions of instructions per second) rate, and execution time for this program.

\text{CPI} = \frac{45000 \times 1 + 32000 \times 2 + 15000 \times 2 + 8000 \times 2}{100000} = \frac{155000}{100000} = 1.55

400,\text{MHz} = 400 ,000 ,000,\text{Hz}

since: \text{MIPS} \propto 1/\text{CPI} and \text{MIPS} \propto \text{clock frequency}

\text{Effective processor performance} = \text{MIPS} = \frac{\text{clock frequency}}{\text{CPI}} \times {\frac{1}{\text{1 Million}}} = \frac{400,000,000 }{1.55 \times 1000000}= \frac{400}{1.55} = 258 , \text{MIPS}

Therefore:

\text{Execution time}(T) = \text{CPI} \times \text{Instruction count} \times \text{clock time} = \frac{\text{CPI} \times \text{Instruction Count}}{\text{frequency}} = \frac{1.55 \times 100000}{400 \times 1000000} = \frac{1.55}{4000} = 0.0003875 , \text{sec} = 0.3875 , \text{ms}

References

References

1. (1994). "Computer Organization and Design: The Hardware/Software Interface". Morgan Kaufmann.
2. Advanced Computer Architecture by Kai Hwang, Chapter 1, Exercise Problem 1.1