Wishbone (computer bus)

| invent-date = | invent-name = Silicore Corporation | super-name = | super-date =

The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores project.

Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels.

This ambiguity is intentional. Wishbone is made to let designers combine several designs written in Verilog, VHDL or some other logic-description language for electronic design automation (EDA). Wishbone provides a standard way for designers to combine these hardware logic designs (called "cores"). Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated combinatorially for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.

Wishbone is open source. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of prior art, to prove its concepts are in the public domain.

A device does not conform to the Wishbone specification unless it includes a data sheet that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others.

The Simple Bus Architecture is a simplified version of the Wishbone specification. Simple Bus Architecture, 2015