RHPPC

Technical details

The RHPPC processor generates 190 MIPS with the Dhrystone mix with its core clock at 100 MHz (i.e. the RHPPC processor completes 1.9 instructions per cycle). The RHPPC runs with a 25, 33.3, 40, or 50 MHz 60x bus clock (SYSCLK) which is generated based on the PCI clock. The 60x bus clock is de-skewed on-chip by a PLL and can also be multiplied.

The RHPPC processor is a superscalar machine with five execution units: system register unit, integer unit, load/store unit, floating point unit, and branch processing unit. The dispatch unit can issue two instructions per cycle. The floating point unit has a three level deep pipeline. Out-of-order execution is supported through the use of shadow or rename registers. The completion unit can complete two instructions per cycle in order by copying results from the rename registers to the real registers. Independently, the branch processing unit can complete a branch each cycle. Thus, in theory, the RHPPC processor can complete three instructions per cycle. Within the RHPPC processor there is a 16 kB instruction and a 16 kB data L1 caches that are 4 way set associative, and support write through or copy-back protocol. A cache line is fixed at eight words.

Fabrication process and packaging

The RHPPC processor is fabricated with Honeywell’s SOI-V 0.35 μm, four level metal process. Standard cells and custom drop-ins are used. It is packaged in a hermetic, aluminium oxide, 21 x 21 mm grid array package with 255 (16 x 16) leads. The leads are on 1.27 mm centers. The lead can have either solder balls, solder columns, or short pins attached. Standard die attach and wire bond die interconnect are used.

References