Priority encoder

Implementation

A truth table of a single bit 4-to-2 priority encoder is shown, where the inputs are shown in decreasing order of priority left-to-right, and "x" indicates a don't care term - i.e. any input value there yields the same output since it is superseded by a higher-priority input. The (usually-included) "v" output indicates if the input is valid.

Priority encoders can be easily connected in arrays to make larger encoders, such as one 16-to-4 encoder made from six 4-to-2 priority encoders – four 4-to-2 encoders having the signal source connected to their inputs, and the two remaining encoders take the output of the first four as input.

Recursive construction of priority encoders

Sources:

A priority-encoder, also called leading zero detector (LZD) or leading zero counter (LZC), receives an n-bit input vector and detects the index of the first binary ‘1’ in the input vector. A valid signal indicates if any binary ‘1’ was detected in the input vector, hence the index is valid.

Priority-encoders can be efficiently constructed by recursion. The input vector is split into k equal fragments with n/k bits. A priority encoder \textrm{PE}{n/k} with a narrower width of 𝑛/𝑘 is applied for each fragment. The valid bit of each of the k \textrm{PE}{n/k}‘s goes to a k bit \textrm{PE}_{n/k} to detect the first valid fragment. The location of this fragment is the higher part of the overall index, and steers the exact location within the fragment itself to produce the lower part of the overall index.

The depth of the proposed structure is \lceil\log_kn\rceil, while the hardware area complexity is \mathcal{O}(n). If Altera's Stratix V or equivalent device is used, k=4 is recommended to achieve higher performance and area compression, since the mux can be implemented using 6-LUT, hence an entire ALM.

An open-source Verilog generator for the recursive priority-encoder is available online.

A behavioral description of priority encoder in Verilog is as follows. In this case, the LSB has the highest priority. // behavioural description of priority enconder; // https://github.com/AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM

module pe_bhv

1. ( parameter OHW = 512 ) // encoder one-hot input width ( input clk , // clock for pipelined priority encoder input rst , // registers reset for pipelined priority encoder input [ OHW -1:0] oht , // one-hot input / [ OHW -1:0] output reg [log2(OHW)-1:0] bin , // first '1' index/ [log2(OHW)-1:0] output reg vld ); // binary is valid if one was found

// use while loop for non fixed loop length // synthesizable well with Intel's QuartusII always @(*) begin bin = {`log2(OHW){1'b0}}; vld = oht[bin] ; while ((!vld) && (bin!=(OHW-1))) begin bin = bin + 1 ; vld = oht[bin]; end end

endmodule

Simple encoder

Main article: Encoder (digital)

A simple encoder circuit is a one-hot to binary converter. That is, if there are 2n input lines, and at most only one of them will ever be high, the binary code of this 'hot' line is produced on the n-bit output lines.

Notes

References

References

1. (2007). "Digital Design". Pearson Prentice Hall.
2. (August 1973). "The TTL Applications Handbook". Fairchild Semiconductor.
3. Abdelhadi, Ameer M. S.. (2016). "Architecture of block-RAM-based massively parallel memory structures : multi-ported memories and content-addressable memories". University of British Columbia.
4. (May 2015). "2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines".
5. (December 2014). "2014 International Conference on Field-Programmable Technology (FPT)".