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List of AMD processors with 3D graphics
None
This is a list of microprocessors designed by AMD containing a 3D integrated graphics processing unit (iGPU), including those under the AMD APU (Accelerated Processing Unit) product series.
Desktop processors with 3D graphics
APU or Radeon Graphics branded
Lynx: "Llano" (2011)
Socket FM1
CPU: K10 (also Husky or K10.5 ) cores with an upgraded Stars architecture, no L3 cache
L1 cache: 64 KB Data per core and 64 KB Instruction cache per core
L2 cache: 512 KB on dual-core, 1 MB on tri- and quad-core models
MMX, Enhanced 3DNow! , SSE, SSE2, SSE3, SSE4a, ABM, NX bit, AMD64, Cool'n'Quiet , AMD-V
GPU: TeraScale 2 (Evergreen); all A and E series models feature Redwood -class integrated graphics on die (BeaverCreek for the dual-core variants and WinterPark for the quad-core variants). Sempron and Athlon models exclude integrated graphics.
List of embedded GPU's
Support for up to four DIMMs of up to DDR3-1866 memory
Fabrication 32 nm on GlobalFoundries SOI process; Die size: , with 1.178 billion transistors
5 GT/s UMI
Integrated PCIe 2.0 controller
Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
Select models support Hybrid Graphics technology to assist a discrete Radeon HD 6450, 6570, or 6670 discrete graphics card. This is similar to the Hybrid CrossFireX technology available in the AMD 700 and 800 chipset series
Model Released Fab Step. CPU GPU DDR3 memory support TDP (W) Box number Part number Cores (threads) Clock rate (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) Base Boost L1 L2 Sempron X2 198 Athlon II X2 221 Athlon II X4 631 Athlon II X4 638 Athlon II X4 641 Athlon II X4 651 Athlon II X4 651K E2-3200 A4-3300 A4-3400 A4-3420 A6-3500 A6-3600 A6-3620 A6-3650 A6-3670K A8-3800 A8-3820 A8-3850 A8-3870K 2012 32 nm SOI LN-B0 2 (2) 2.5 rowspan=12 64 KB inst. 64 KB data per core 2×512 KB rowspan=8 colspan=4 1600 65 SD198XOJGXBOX SD198XOJZ22GX 2012 2.8 AD221XOJGXBOX AD221XOJZ22GX 2012 4 (4) 2.6 4×1 MB 1866 AD631XOJGXBOX AD631XOJZ43GX Aug 15, 2011 100 AD631XOJGXBOX AD631XWNZ43GX Feb 8, 2012 2.7 65 AD638XOJGXBOX AD638XOJZ43GX Feb 8, 2012 2.8 100 AD641XWNGXBOX AD641XWNZ43GX Nov 14, 2011 3.0 AD651XWNGXBOX AD651XWNZ43GX 2012 AD651KWNGXBOX AD651KWNZ43GX 2011 2 (2) 2.4 2×512 KB HD 6370D 160:8:4 443 141.7 1600 65 ED3200OJGXBOX ED3200OJZ22GX ED3200OJZ22HX Sep 7, 2011 2.5 HD 6410D AD3300OJGXBOX AD3300OJHXBOX AD3300OJZ22GX AD3300OJZ22HX Sep 7, 2011 2.7 600 192 AD3400OJGXBOX AD3400OJHXBOX AD3400OJZ22GX AD3400OJZ22HX Dec 20, 2011 2.8 AD3420OJZ22HX Aug 17, 2011 3 (3) 2.1 2.4 3×1 MB HD 6530D 320:16:8 443 283.5 1866 AD3500OJGXBOX AD3500OJZ33GX Aug 17, 2011 4 (4) 4×1 MB AD3600OJGXBOX AD3600OJZ43GX Dec 20, 2011 2.2 2.5 AD3620OJGXBOX AD3620OJZ43GX Jun 30, 2011 2.6 rowspan=2 100 AD3650WNGXBOX AD3650WNZ43GX Dec 20, 2011 2.7 AD3670WNGXBOX AD3670WNZ43GX Aug 17, 2011 2.4 2.7 HD 6550D 400:20:8 600 480 65 AD3800OJGXBOX AD3800OJZ43GX Dec 20, 2011 2.5 2.8 AD3820OJGXBOX AD3820OJZ43GX Jun 30, 2011 2.9 rowspan=2 100 AD3850WNGXBOX AD3850WNZ43GX Dec 20, 2011 3.0 AD3870WNGXBOX AD3870WNZ43GX
Virgo: "Trinity" (2012)
Fabrication 32 nm on GlobalFoundries SOI process
Socket FM2
CPU: Piledriver
L1 Cache: 16 KB Data per core and 64 KB Instructions per module
GPU TeraScale 3 (VLIW4)
Die Size: , 1.303 Billion transistors
Support for up to four DIMMs of up to DDR3-1866 memory
5 GT/s UMI
GPU (based on VLIW4 architecture) instruction support: DirectX 11, Opengl 4.2, DirectCompute, Pixel Shader 5.0, Blu-ray 3D, OpenCL 1.2, AMD Stream, UVD3
Integrated PCIe 2.0 controller, and Turbo Core technology for faster CPU/GPU operation when the thermal specification permits
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM
Sempron and Athlon models exclude integrated graphics
Select models support Hybrid Graphics technology to assist a Radeon HD 7350, 7450, 7470, 7550, 7570, 7670 discrete graphics card. However, it has been found that this does not always improve 3D accelerated graphics performance.
Model Released Fab Step. CPU GPU DDR3 memory support TDP (W) Box number Part number Modules/[FPUs] Cores/threads Clock rate (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) Base Boost L1 L2 Sempron X2 240 Athlon X2 340 Athlon X4 730 Athlon X4 740 Athlon X4 750K FirePro A300 FirePro A320 A4-5300 A4-5300B A6-5400K A6-5400B A8-5500 A8-5500B A8-5600K A10-5700 A10-5800K A10-5800B 32 nm TN-A1 [1]2 2.9 3.3 64 KB inst. per module 16 KB data per core 1 MB rowspan=5 colspan=4 1600 65 SD240XOKA23HJ Oct 2012 3.2 3.6 AD340XOKA23HJ Oct 1, 2012 [2]4 2.8 3.2 2×2 MB 1866 AD730XOKA44HJ Oct 2012 3.2 3.7 AD740XOKHJBOX AD740XOKA44HJ 3.4 4.0 100 AD750KWOHJBOX AD750KWOA44HJ Aug 7, 2012 3.4 4.0 FirePro 384:24:8 6 CU 760 583.6 65 AWA300OKA44HJ 3.8 4.2 800 614.4 100 AWA320WOA44HJ Oct 1, 2012 [1]2 3.4 3.6 1 MB HD 7480D 128:8:4 2 CU 723 185 1600 65 AD5300OKHJBOX AD5300OKA23HJ Oct 2012 AD530BOKA23HJ Oct 1, 2012 3.6 3.8 HD 7540D 192:12:4 3 CU 760 291.8 1866 AD540KOKHJBOX AD540KOKA23HJ Oct 2012 AD540BOKA23HJ Oct 1, 2012 [2]4 3.2 3.7 2×2 MB HD 7560D 256:16:8 4 CU 760 389.1 AD5500OKHJBOX AD5500OKA44HJ Oct 2012 AD550BOKA44HJ Oct 1, 2012 3.6 3.9 100 AD560KWOHJBOX AD560KWOA44HJ 3.4 4.0 HD 7660D 384:24:8 6 CU 760 583.6 65 AD5700OKHJBOX AD5700OKA44HJ 3.8 4.2 800 614.4 100 AD580KWOHJBOX AD580KWOA44HJ Oct 2012 AD580BWOA44HJ
"Richland" (2013)
Fabrication 32 nm on GlobalFoundries SOI process
Socket FM2
Two or four CPU cores based on the Piledriver microarchitecture
Die Size: , 1.303 Billion transistors
L1 Cache: 16 KB Data per core and 64 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, AVX, AVX1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core 3.0, NX bit, PowerNow!
GPU
TeraScale 3 architecture
HD Media Accelerator, AMD Hybrid Graphics
Model Released Fab Step. CPU GPU DDR3 memory support TDP (W) Box number Part number Modules/[FPUs] Cores/threads Clock rate (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) Base Boost L1 L2 Sempron X2 250 Athlon X2 350 Athlon X2 370K Athlon X4 750 Athlon X4 760K FX-670K A4-4000 A4-4020 A4-6300 A4-6300B A4-6320 A4-6320B A4-7300 A6-6400B A6-6400K A6-6420B A6-6420K A8-6500T A8-6500 A8-6500B A8-6600K A10-6700T A10-6700 A10-6790B A10-6790K A10-6800K A10-6800B 32 nm RL-A1 [1]2 3.2 3.6 64 KB inst. per module 16 KB data per core 1 MB rowspan=6 colspan=4 65 SD250XOKA23HL 3.5 3.9 1866 AD350XOKA23HL Jun 2013 4.0 4.2 AD370KOKHLBOX AD370KOKA23HL Oct 2013 [2]4 3.4 4.0 2×2 MB AD750XOKA44HL Jun 2013 3.8 4.1 100 AD760KWOHLBOX AD760KWOA44HL Mar 2014 (OEM) 3.7 4.3 65 FD670KOKA44HL May 2013 [1]2 3.0 3.2 1 MB HD 7480D 128:8:4 2 CU 720 184.3 1333 AD4000OKHLBOX AD4000OKA23HL Jan 2014 3.2 3.4 AD4020OKHLBOX AD4020OKA23HL Jul 2013 3.7 3.9 HD 8370D 760 194.5 1600 AD6300OKHLBOX AD6300OKA23HL AD630BOKA23HL Dec 2013 3.8 4.0 AD6320OKHLBOX AD6320OKA23HL Mar 2014 AD632BOKA23HL Aug 2014 HD 8470D 192:12:4 3 CU 800 307.2 AD7300OKA23HL A4 Pro-7300B AD730BOKA23HL Jun 4, 2013 3.9 4.1 1866 AD640BOKA23HL AD640KOKHLBOX AD640KOKA23HL Jan 2014 4.0 4.2 AD642BOKA23HL AD642KOKHLBOX AD642KOKA23HL Sep 18, 2013 [2]4 2.1 3.1 2×2 MB HD 8550D 256:16:8 4 CU 720 368.6 45 AD650TYHHLBOX AD650TYHA44HL Jun 4, 2013 3.5 4.1 HD 8570D 800 409.6 65 AD6500OKHLBOX AD6500OKA44HL AD650BOKA44HL 3.9 4.2 844 432.1 100 AD660KWOHLBOX AD660KWOA44HL Sep 18, 2013 2.5 3.5 HD 8650D 384:24:8 6 CU 720 552.9 45 AD670TYHHLBOX AD670TYHA44HL Jun 4, 2013 3.7 4.3 HD 8670D 844 648.1 65 AD6700OKHLBOX AD6700OKA44HL Oct 29, 2013 4.0 100 AD679KWOHLBOX AD679KWOA44HL Oct 28, 2013 AD679BWOA44HL Jun 4, 2013 4.1 4.4 2133 AD680KWOHLBOX AD680KWOA44HL AD680BWOA44HL
"Kabini" (2013, [[System on a chip|SoC]])
Fabrication 28 nm by GlobalFoundries
Socket AM1, aka Socket FS1b (AM1 platform)
2 to 4 CPU Cores (Jaguar (microarchitecture))
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
SoC with integrated memory, PCIe, 2× USB 3.0, 6× USB 2.0, Gigabit Ethernet, and 2× SATA III (6 Gb/s) controllers
GPU based on Graphics Core Next (GCN)
Model Released Fab Step. CPU GPU DDR3 memory support TDP (W) Box number Part number Cores (threads) Clock rate (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) Base Boost L1 L2 Athlon X4 530 Athlon X4 550 Sempron 2650 Sempron 3850 Athlon 5150 Athlon 5350 Athlon 5370 28 nm KB-A1 4 (4) 2.00 rowspan="7" 32 KB inst. 32 KB data per core 2 MB rowspan="2" colspan="4" 1600 single-channel 25 AD530XJAH44HM 2.20 AD550XJAH44HM Apr 9, 2014 2 (2) 1.45 1 MB R3 (HD 8240) 128:8:4 2 CU 400 102.4 1333 single-channel SD2650JAHMBOX SD2650JAH23HM 4 (4) 1.30 2 MB R3 (HD 8280) 450 115.2 1600 single-channel SD3850JAHMBOX SD3850JAH44HM 1.60 R3 (HD 8400) 600 153.6 AD5150JAHMBOX AD5150JAH44HM 2.05 AD5350JAHMBOX AD5350JAH44HM Feb 2016 2.20 AD5370JAH44HM
"Kaveri" (2014) & "Godavari" (2015)
Fabrication 28 nm by GlobalFoundries.
Socket FM2+, support for PCIe 3.0.
Two or four CPU cores based on the Steamroller microarchitecture.
Kaveri refresh models have codename Godavari.
Die Size: , 2.41 Billion transistors.
L1 Cache: 16 KB Data per core and 96 KB Instructions per module.
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
Three to eight Compute Units (CUs) based on GCN 2nd gen microarchitecture; 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1 Render Output Unit (ROPs).
Heterogeneous System Architecture-enabled zero-copy through pointer passing.
SIP blocks: Unified Video Decoder, Video Coding Engine, TrueAudio.
Dual-channel (2× 64 Bit) DDR3 memory controller.
Integrated custom ARM Cortex-A5 co-processor with TrustZone Security Extensions in select APU models, except the Performance APU models.
Select models support Hybrid Graphics technology by using a Radeon R7 240 or R7 250 discrete graphics card.
Display controller: AMD Eyefinity 2, 4K Ultra HD support, DisplayPort 1.2 Support.
Model Released Fab Step. CPU GPU DDR3 memory support TDP (W) Box number Part number Modules/[FPUs] Cores/threads Clock rate (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) Base Boost L1 L2 Athlon X2 450 Athlon X4 830 Athlon X4 840 Athlon X4 850 Athlon X4 860K Athlon X4 870K Athlon X4 880K FX-770K A4 Pro-7350B Pro A4-8350B A6-7400K A6 Pro-7400B A6-7470K Pro A6-8550B A8-7500 A8-7600 A8 Pro-7600B A8-7650K A8-7670K Pro A8-8650B A10-7700K A10-7800 A10 PRO-7800B A10-7850K A10 Pro-7850B A10-7860K A10-7870K A10-7890K Pro A10-8750B Pro A10-8850B Model Released Fab Step. [Modules/FPUs] Cores/threads Base Boost L1 L2 Model Config Clock (MHz) Processing power (GFLOPS) DDR3 memory support TDP (W) Box number Part number Clock rate (GHz) Cache CPU GPU Jul 31, 2014 28 nm KV-A1 [1]2 3.5 3.9 96 KB inst. per module 16 KB data per core 1 MB rowspan=8 colspan=4 1866 65 AD450XYBI23JA 2018 [2]4 3.0 3.4 2×2 MB 2133 AD830XYBI44JA Aug 2014 3.1 3.8 AD840XYBJABOX AD840XYBI44JA 2015 GV-A1 3.2 AD835XACI43KA Aug 2014 KV-A1 3.7 4.0 95 AD860KXBJABOX AD860KWOHLBOX AD860KXBJASBX AD860KXBI44JA Dec 2015 GV-A1 3.9 4.1 AD870KXBJCSBX AD870KXBI44JC Mar 1, 2016 4.0 4.2 AD880KXBJCSBX Dec 2014 KV-A1 3.5 3.9 65 FD770KYBI44JA Jul 31, 2014 [1]2 3.4 3.8 1 MB R5 192:12:8 3 CU 514 197.3 1866 AD735BYBI23JA Sep 29, 2015 3.5 3.9 256:16:8 4 CU 757 387.5 AD835BYBI23JC Jul 31, 2014 3.5 3.9 756 387 AD740KYBJABOX AD740KYBI23JA AD740BYBI23JA Feb 2, 2016 GV-A1 3.7 4.0 800 409.6 2133 AD747KYBJCBOX AD747KYBI23JC Sep 29, 2015 AD855BYBI23JC 2014 KV-A1 [2]4 3.0 3.7 2×2 MB R7 384:24:8 6 CU 720 552.9 AD7500YBI44JA Jul 31, 2014 3.1 3.8 AD7600YBJABOX AD7600YBI44JA AD760BYBI44JA Jan 7, 2015 3.3 95 AD765KXBJABOX AD765KXBJASBX AD765KXBI44JA Jul 20, 2015 GV-A1 3.6 3.9 757 581.3 AD767KXBJCSBX AD767KXBJCBOX AD767KXBI44JC Sep 29, 2015 3.2 65 AD865BYBI44JC Jan 14, 2014 KV-A1 3.4 3.8 720 552.9 95 AD770KXBJABOX AD770KXBI44JA Jul 31, 2014 3.5 3.9 512:32:8 8 CU 737.2 65 AD7800YBJABOX AD7800YBI44JA AD780BYBI44JA Jan 14, 2014 3.7 4.0 95 AD785KXBJABOX AD785KXBI44JA Jul 31, 2014 AD785BXBI44JA Feb 2, 2016 GV-A1 3.6 757 775.1 65 AD786KYBJABOX AD786KYBJCSBX AD786KYBI44JC May 28, 2015 3.9 4.1 866 886.7 95 AD787KXDJCBOX AD787KXDJCSBX AD787KXDI44JC Mar 1, 2016 4.1 4.3 AD789KXDJCHBX AD789KXDI44JC Sep 29, 2015 3.6 4.0 757 775.1 65 AD875BYBI44JC 3.9 4.1 800 819.2 95 AD885BXBI44JC
"Carrizo" (2016)
Fabrication: 28 nm by GlobalFoundries
Socket FM2+ or AM4, support for PCIe 3.0
Two or four CPU cores based on the Excavator microarchitecture
Die size: , 3.1 billion transistors
L1 cache: 32 KB data per core and 96 KB instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
Single- or dual-channel DDR3 or DDR4 memory controller
Third generation GCN-based GPU (Radeon M300)
Integrated custom ARM Cortex-A5 coprocessor with TrustZone security extensions
Model Released Fab Step. Socket CPU GPU Memory support TDP (W) Box number Part number Modules/[FPUs] Cores/threads Clock rate (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) Base Boost L1 L2 Athlon X4 835 Athlon X4 845 A6-7480 A8-7680 Pro A6-8570E Pro A6-8570 Pro A10-8770E Pro A10-8770 Pro A12-8870E Pro A12-8870 28 nm CZ-A1 FM2+ [2]4 3.1 96 KB inst. per module 32 KB data per core 2×1 MB rowspan="2" colspan="4" DDR3-2133 65 AD835XACI43KA Feb 2, 2016 3.5 3.8 AD845XYBJCSBX AD845XACKASBX AD845XACI43KA Oct 2018 [1]2 1 MB R5 384:24:8 6 CU 900 691.2 AD7480ACABBOX AD7480ACI23AB [2]4 2×1 MB R7 AD7680ACABBOX AD7680ACI43AB Oct 2016 AM4 [1]2 3.0 3.4 1 MB R5 256:16:4 4 CU 800 409.6 DDR4-2400 35 AD857BAHM23AB 3.5 3.8 384:24:6 6 CU 1029 790.2 65 AD857BAGM23AB [2]4 2.8 3.5 2×1 MB R7 847 650.4 35 AD877BAHM44AB 3.5 3.8 1029 790.2 65 AD877BAGM44AB 2.9 512:32:8 8 CU 900 921.6 35 AD887BAHM44AB 3.7 4.2 1108 1134.5 65 AD887BAUM44AB
"Bristol Ridge" (2016)
Fabrication 28 nm by GlobalFoundries
Socket AM4, support for PCIe 3.0
Two or four "Excavator+" CPU cores
L1 Cache: 32 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
Dual-channel DDR4 memory controller
PCI Express 3.0 x8 (No Bifurcation support, requires a PCI-e switch for any configuration other than x8)
PCI Express 3.0 x4 as link to optional external chipset
4x USB 3.1 Gen 1
Storage: 2x SATA and 2x NVMe or 2x PCI Express
Third Generation GCN based GPU with hybrid VP9 decoding
Model Released Fab Step. CPU GPU DDR4 memory support TDP (W) Box number Part number Modules/[FPUs] Cores/threads Clock rate (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) Base Boost L1 L2 Athlon X4 940 Athlon X4 950 Athlon X4 970 A6-9400 A6-9500E Pro A6-9500E A6-9500 Pro A6-9500 A6-9550 A8-9600 Pro A8-9600 A10-9700E Pro A10-9700E A10-9700 Pro A10-9700 A12-9800E Pro A12-9800E A12-9800 Pro A12-9800 Jul 27, 2017 28 nm BR-A1 [2]4 3.2 3.6 96 KB inst. per module 32 KB data per core 2×1 MB rowspan=3 colspan=4 2400 65 AD940XAGABBOX AD940XAGM44AB 3.5 3.8 AD950XAGABBOX AD950XAGM44AB 3.8 4.0 AD970XAUABBOX AD970XAUM44AB Mar 16, 2019 [1]2 3.4 3.7 1 MB R5 192:12:4 3 CU 720 276.4 AD9400AGABBOX AD9400AGM23AB Sep 5, 2016 3.0 3.4 256:16:4 4 CU 800 409.6 35 AD9500AHABBOX AD9500AHM23AB Oct 3, 2016 AD950BAHM23AB Sep 5, 2016 3.5 3.8 384:24:6 6 CU 1029 790.2 65 AD9500AGABBOX AD9500AGM23AB Oct 3, 2016 AD950BAGM23AB Jul 27, 2017 3.8 4.0 256:16:4 4 CU 800 409.6 AD9550AGABBOX AD9550AGM23AB Sep 5, 2016 [2]4 3.1 3.4 2×1 MB R7 384:24:6 6 CU 900 691.2 AD9600AGABBOX AD9600AGM44AB Oct 3, 2016 AD960BAGM44AB Sep 5, 2016 3.0 3.5 847 650.4 35 AD9700AHABBOX AD9700AHM44AB Oct 3, 2016 AD970BAHM44AB Sep 5, 2016 3.5 3.8 1029 790.2 65 AD9700AGABBOX AD9700AGM44AB Oct 3, 2016 AD970BAGM44AB Sep 5, 2016 3.1 3.8 512:32:8 8 CU 900 921.6 35 AD9800AHABBOX AD9800AUM44AB Oct 3, 2016 AD980BAHM44AB Sep 5, 2016 3.8 4.2 1108 1134.5 65 AD9800AUABBOX AD9800AUM44AB Oct 3, 2016 AD980BAUM44AB
"Raven Ridge" (2018)
Main article: Ryzen
Fabrication 14 nm by GlobalFoundries
Transistors: 4.94 billion
Die size: 210 mm2
Socket AM4
Zen CPU cores
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Dual-channel DDR4 memory controller
Fifth generation GCN based GPU
Video Core Next (VCN) 1.0
"Picasso" (2019)
Main article: Ryzen
Fabrication 12 nm by GlobalFoundries
Transistors: 4.94 billion
Die size: 210 mm2
Socket AM4
Zen+ CPU cores
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Dual-channel DDR4 memory controller
Fifth generation GCN based GPU
Video Core Next (VCN) 1.0
"Renoir" (2020)
Main article: Ryzen
Fabrication 7 nm by TSMC
Socket AM4
Up to eight Zen 2 CPU cores
Dual-channel DDR4 memory controller
"Cezanne" (2021)
Main article: Ryzen
Fabrication 7 nm by TSMC
Socket AM4
Up to eight Zen 3 CPU cores
Dual-channel DDR4 memory controller
Non APU or Radeon Graphics branded
"Raphael" (2022)
Main article: Ryzen
Fabrication 5 nm (CCD) and 6 nm (cIOD) by TSMC
Socket AM5
Up to sixteen Zen 4 CPU cores
Dual-channel DDR5 memory controller
Basic iGPU
"Phoenix" (2024)
Server APUs
Opteron X2100-series "Kyoto" (2013) & "Steppe Eagle" (2016)
Fabrication 28 nm
Socket FT3 (BGA)
4 CPU Cores (Jaguar & Puma microarchitecture)
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
Single-channel DDR3 memory controller
Turbo Dock Technology, C6 and CC6 low power states
GPU based on 2nd generation Graphics Core Next (GCN) architecture
Model Released Fab Step. CPU GPU DDR3 memory support TDP (W) Part number Release price (USD) Cores (threads) Clock (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) L1 L2 X1150 X2150 X2170 May 29, 2013 28 nm 4 (4) 2.0 32 KB inst. 32 KB data per core 2 MB colspan="4" 1600 9–17 OX1150IPJ44HM $64 1.9 R3 (HD 8400) 128:8:4 2 CU 266–600 28.9 11–22 OX2150IAJ44HM $99 Sep 1, 2016 2.4 R5 655–800 153.6 1866 11–25 OX2170IXJ44JB
Opteron X3000-series "Toronto" (2017)
Fabrication 28 nm
Socket FP4 (BGA)
Two or Four CPU cores based on the Excavator microarchitecture
L1 Cache: 32 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
Dual-channel DDR4 memory controller
GPU based on 3rd generation Graphics Core Next (GCN) architecture
Model Released Fab Step. CPU GPU DDR4 memory support TDP (W) Part number Release price (USD) Modules/[FPUs] Cores/threads Clock rate (GHz) Cache Model Config Clock (MHz) Processing power (GFLOPS) Base Boost L1 L2 X3216 X3418 X3421 June 2017 28 nm 01h [1]2 1.6 3.0 96 KB inst. per module 32 KB data per core 1 MB R5 256:16:4 4 CU 800 409.6 1600 12–15 OX3216AAY23KA OEM for HP [2]4 1.8 3.2 2 MB R6 384:24:6 6 CU 614.4 2400 12–35 OX3418AAY43KA June 2017 2.1 3.4 R7 512:32:8 8 CU 819.2 OX3421AAY43KA
Mobile processors with 3D graphics
APU or Radeon Graphics branded
Sabine: "Llano" (2011)
Fabrication 32 nm on GlobalFoundries SOI process
Socket FS1
Upgraded Stars (AMD 10h architecture) codenamed Husky CPU cores (K10.5) with no L3 cache, and with Redwood -class integrated graphics on die
L1 Cache: 64 KB Data per core and 64 KB Instructions per core(BeaverCreek for the dual-core variants and WinterPark for the quad-core variants)
Integrated PCIe 2.0 controller
GPU: TeraScale 2
Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
Support for 1.35 V DDR3L-1333 memory, in addition to regular 1.5 V DDR3 memory specified
2.5 GT/s UMI
MMX, Enhanced 3DNow! , SSE, SSE2, SSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
PowerNow!
Model Released Fab Step. CPU GPU DDR3 TDP Part number Cores (threads) Clock Turbo Cache Model Config Clock GFLOPS L1 L2 L3 E2-3000M colspan="2" colspan="4" colspan="2" A4-3300M A4-3305M A4-3310MX A4-3320M A4-3330MX A4-3330MX colspan="3" colspan="4" colspan="2" A6-3400M A6-3410MX A6-3420M A6-3430MX colspan="2" colspan="7" A8-3500M A8-3510MX A8-3520M A8-3530MX A8-3550MX 2011 32 nm B0 2 (2) 1.8 2.4 64 KB inst. 64 KB data per core 2× 512KB rowspan=19 HD 6380G 160:8:4 400 128 1333 35 EM3000DDX22GX 2011 1.9 2.5 2× 1MB HD 6480G 240:12:4 444 213.1 35 AM3300DDX23GX December 7, 2011 2× 512KB 160:8:4 593 189.7 AM3305DDX22GX 2011 2.1 2× 1MB 240:12:4 444 213.1 45 AM3310HLX23GX December 7, 2011 2.0 2.6 35 AM3320DDX23GX 2.2 45 AM3330HLX23GX 2.3 2× 512KB 160:8:4 593 189.7 AM3330HLX23HX 2011 4 (4) 1.4 2.3 4× 1MB HD 6520G 320:16:8 400 256 35 AM3400DDX43GX 1.6 1600 45 AM3410HLX43GX December 7, 2011 1.5 2.4 1333 35 AM3420DDX43GX 1.7 1600 45 AM3430HLX43GX 2011 1.5 2.4 HD 6620G 400:20:8 444 355.2 1333 35 AM3500DDX43GX 1.8 2.5 1600 45 AM3510HLX43GX December 7, 2011 1.6 1333 35 AM3520DDX43GX 2011 1.9 2.6 1600 45 AM3530HLX43GX December 7, 2011 2.0 2.7 AM3550HLX43GX
Comal: "Trinity" (2012)
An AMD A10-4600M APU
Fabrication 32 nm on GlobalFoundries SOI process
Socket FS1r2, FP2
Based on the Piledriver architecture
L1 Cache: 16 KB Data per core and 64 KB Instructions per module
GPU: TeraScale 3 (VLIW4)
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
Memory support: 1.35 V DDR3L-1600 memory, in addition to regular 1.5 V DDR3 memory specified (Dual-channel)
2.5 GT/s UMI
Transistors: 1.303 billion
Die size: 246 mm2
Model number Released Fab Step. Socket CPU GPU DDR3 TDP Part number Modules/[FPUs] Clock Turbo Cache Model Config Clock Turbo GFLOPS L1 L2 A4-4355M A6-4455M A8-4555M A8-4557M A10-4655M A10-4657M colspan="4" colspan="6" A4-4300M A6-4400M A8-4500M A10-4600M September 27, 2012 32 nm TN-A1 FP2 [1]2 1.9 2.4 64 KB inst. per module 16 KB data per core 1 HD 7400G 192:12:4 3 CU 327 424 125.5 1333 17 AM4355SHE23HJ May 15, 2012 2.1 2.8 2 HD 7500G 256:16:8 4 CU 167.4 AM4455SHE24HJ September 27, 2012 [2]4 1.6 2.4 2× HD 7600G 384:24:8 6 CU 320 245.7 19 AM4555SHE44HJ Mar 1.9 2.8 HD 7000 256:16:8 4 CU 497 655 254.4 (L)1600 35 AM4557DFE44HJ May 15, 2012 2.0 2.8 HD 7620G 384:24:8 6 CU 360 496 276.4 1333 25 AM4655SIE44HJ Mar 2.3 3.2 HD 7000 497 686 381.6 (L)1600 35 AM4657DFE44HJ May 15, 2012 FS1r2 [1]2 2.5 3.0 1 HD 7420G 128:8:4 2 CU 480 655 122.8 1600 AM4300DEC23HJ 2.7 3.2 HD 7520G 192:12:4 3 CU 496 685 190.4 AM4400DEC23HJ [2]4 1.9 2.8 2× HD 7640G 256:16:8 4 CU 253.9 AM4500DEC44HJ 2.3 3.2 HD 7660G 384:24:8 6 CU 380.9 AM4600DEC44HJ
"Richland" (2013)
Fabrication 32 nm on GlobalFoundries SOI process
Socket FS1r2, FP2
Elite Performance APU .CPU: Piledriver architecture
L1 Cache: 16 KB Data per core and 64 KB Instructions per module
GPU: TeraScale 3 (VLIW4)
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
Model number Released Fab Step. Socket CPU GPU DDR3 TDP Part number Modules/[FPUs] Clock Turbo Cache Model Config Clock Turbo GFLOPS L1 L2 A4-5145M A6-5345M A8-5545M A10-5745M colspan="8" A4-5150M A6-5350M A6-5357M A8-5550M A8-5557M A10-5750M A10-5757M 2013/5 32 nm RL-A1 FP2 [1]2 2.0 2.6 64 KB inst. per module 16 KB data per core 1 HD 8310G 128:8:4 2 CU 424 554 108.5 (L)1333 17 AM5145SIE44HL 2.2 2.8 HD 8410G 192:12:4 3 CU 450 600 172.8 AM5345SIE44HL [2]4 1.7 2.7 4 HD 8510G 384:28:8 6 CU 554 345.6 19 AM5545SIE44HL 2.1 2.9 HD 8610G 533 626 409.3 25 AM5745SIE44HL 2013 Q1 FS1r2 [1]2 2.7 3.3 1 HD 8350G 128:8:4 2 CU 533 720 136.4 1600 35 AM5150DEC23HL 2.9 3.5 HD 8450G 192:12:4 3 CU 204.6 AM5350DEC23HL 2013/5 FP2 (L)1600 AM5357DFE23HL 2013 Q1 FS1r2 [2]4 2.1 3.1 4 HD 8550G 256:16:8 4 CU 515 263.6 1600 AM5550DEC44HL 2013/5 FP2 554 283.6 (L)1600 AM5557DFE44HL 2013 Q1 FS1r2 2.5 3.5 HD 8650G 384:24:8 6 CU 533 409.3 1866 AM5750DEC44HL 2013/5 FP2 600 460.8 (L)1600 AM5757DFE44HL
"Kaveri" (2014)
Fabrication 28 nm
Socket FP3
Up to 4 Steamroller x86 CPU cores with 4 MB of L2 cache.
L1 Cache: 16 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
Three to eight Compute Units (CUs) based on Graphics Core Next (GCN) microarchitecture; 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1 Render Output Unit (ROPs)
AMD Heterogeneous System Architecture (HSA) 2.0
SIP blocks: Unified Video Decoder, Video Coding Engine, TrueAudio
Dual-channel (2x64-bit) DDR3 memory controller
Integrated custom ARM Cortex-A5 co-processor with TrustZone Security Extensions
Model number Released Fab CPU GPU DDR3 TDP Part number Modules/[FPUs] Clock Turbo Cache Model Config Clock Turbo GFLOPS L1 L2 A6-7000 A6 PRO - 7050B colspan="3" colspan="8" A8-7100 A8 PRO - 7150B A10-7300 A10 PRO - 7350B FX-7500 colspan="2" colspan="7" A8-7200P A10-7400P FX-7600P June 2014 28 nm [1]2 2.2 3.0 96 KB inst. per module 16 KB data per core 1 R4 192:12:3 3 CU 494 533 189.6 1333 17 AM7000ECH23JA 533 204.6 1600 AM705BECH23JA [2]4 1.8 3.0 2× 2 MB R5 256:16:4 4 CU 450 514 230.4 1600 20 AM7100ECH44JA 1.9 3.2 553 283.1 AM715BECH44JA R6 384:24:8 6 CU 464 533 356.3 AM7300ECH44JA 2.1 3.3 533 424.7 AM735BECH44JA R7 498 553 382.4 FM7500ECH44JA 2.4 3.3 R5 256:16:4 4 CU 553 626 283.1 1866 35 AM740PDGH44JA 2.5 3.4 R6 384:24:8 6 CU 576 654 442.3 AM740PDGH44JA 2.7 3.6 R7 512:32:8 8 CU 600 686 614.4 2133 FM760PDGH44JA
"Carrizo" (2015)
Fabrication 28 nm
Socket FP4
Up to 4 Excavator x86 CPU cores
L1 Cache: 32 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
GPU based on Graphics Core Next 1.2
Model number Released Fab CPU GPU DDR TDP Part number Modules/[FPUs] Clock Turbo Cache Model Config Clock GFLOPS L1 L2 A6-8500P PRO A6-8500B PRO A6-8530B colspan="3" colspan="2" A8-8600P PRO A8-8600B A10-8700P PRO A10-8700B PRO A10-8730B A10-8780P FX-8800P PRO A12-8800B PRO A12-8830B June 2015 28 nm [1]2 1.6 3.0 96 KB inst. per module 32 KB data per core 1 R5 256:16:4 4 CU 800 409.6 3)1600 12- AM850PAAY23KA AM850BAAY23KA Q3 2016 2.3 3.2 4)1866 AM853BADY23AB June 2015 [2]4 1.6 3.0 2× R6 384:24:8 6 CU 720 552.9 3)2133 AM860PAAY43KA AM860BAAY43KA 1.8 3.2 800 614.4 AM870PAAY43KA AM870BAAY43KA Q3 2016 2.4 3.3 R5 720 552.9 4)1866 AM873BADY44AB December 2015 2.0 3.3 R8 512:32:8 8 CU 3)? AM878PAIY43KA June 2015 2.1 3.4 R7 800 819.2 4)2133 FM880PAAY43KA FM880BAAY43KA Q3 2016 2.5 3.4 384:24:8 6 CU 758 582.1 4)1866 AM883BADY44AB
"Bristol Ridge" (2016)
Fabrication 28 nm
Socket FP4
Two or four "Excavator+" x86 CPU cores
L1 Cache: 32 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
GPU based on Graphics Core Next 1.2 with VP9 decoding
"Raven Ridge" (2017)
Main article: Ryzen
Fabrication 14 nm by GlobalFoundries
Transistors: 4.94 billion
Socket FP5
Die size: 210 mm2
Zen CPU cores
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Fifth generation GCN-based GPU
"Picasso" (2019)
Main article: Ryzen
Fabrication 12 nm by GlobalFoundries
Socket FP5
Die size: 210 mm2
Up to four Zen+ CPU cores
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Dual-channel DDR4 memory controller
Fifth generation GCN-based GPU
"Renoir" (2020)
Main article: Ryzen
Fabrication 7 nm by TSMC
Socket FP6
Die size: 156 mm2
9.8 billion transistors on one single 7 nm monolithic die
Up to eight Zen 2 CPU cores
L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
L2 cache: 512 KB per core.
Fifth generation GCN-based GPU
Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
All the CPUs support 16 PCIe 3.0 lanes.
U
H
"Lucienne" (2021)
Main article: Ryzen
Fabrication 7 nm by TSMC
Socket FP6
Die size: 156 mm2
9.8 billion transistors on one single 7 nm monolithic die
Up to eight Zen 2 CPU cores
Fifth generation GCN-based GPU (7 nm Vega)
"Cezanne" (2021)
Main article: Ryzen
Fabrication 7 nm by TSMC
Socket FP6
Die size: 180 mm2
Up to eight Zen 3 CPU cores
L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
L2 cache: 512 KB per core.
Fifth generation GCN-based GPU
Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
All the CPUs support 16 PCIe 3.0 lanes.
U
H
"Barceló" (2022)
Main article: Ryzen
Fabrication 7 nm by TSMC
Socket FP6
Die size: 180 mm2
Up to eight Zen 3 CPU cores
L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
L2 cache: 512 KB per core.
Fifth generation GCN-based GPU
Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
All the CPUs support 16 PCIe 3.0 lanes.
"Rembrandt" (2022)
Main article: Ryzen
Fabrication 6 nm by TSMC
Socket FP7
Die size: 210 mm2
Up to eight Zen 3+ CPU cores
Second generation RDNA-based GPU
"Phoenix" (2024)
Main article: Ryzen
Fabrication 4 nm by TSMC
Up to eight Zen 4 CPU cores
Dual-channel DDR5 or LPDDR5x memory controller
RDNA3 iGPU
XDNA accelerator
"Dragon Range" (2023)
Main article: Ryzen
Fabrication 5 nm (CCD) and 6 nm (cIOD) by TSMC
Up to sixteen Zen 4 CPU cores
Dual-channel DDR5 memory controller
Basic RDNA2 iGPU
Ultra-mobile APUs
Brazos: "Desna", "Ontario", "Zacate" (2011) ===
Fabrication 40 nm by TSMC
Socket FT1 (BGA-413)
Based on the Bobcat microarchitecture
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
PowerNow!
DirectX 11 integrated graphics with UVD 3.0
Z-series denote Desna ; C-series denote Ontario ; and the E-series denotes Zacate
2.50 GT/s UMI (PCIe 1.0 ×4)
Model Released Fab Step. CPU GPU DDR3 TDP Part number Cores (threads) Clock Turbo Cache Model Config Clock Turbo GFLOPS L1 L2 Z-01 colspan="2" colspan="2" C-30 C-50 C-60 colspan="6" E-240 E-300 E-350 E-450 June 1, 2011 40 nm B0 2 (2) 1.0 rowspan=4 32KB inst. 32KB data per core 2× 512KB HD 6250 80:8:4 276 rowspan=4 44.1 1066 5.9 XMZ01AFVB22GV January 4, 2011 1 (1) 1.2 512KB 9 CMC30AFPB12GT 2 (2) 1.0 2× 512KB CMC50AFPB22GT August 22, 2011 C0 1.33 HD 6290 400 CMC60AFPB22GV January 4, 2011 B0 1 (1) 1.5 rowspan=4 512KB HD 6310 500 rowspan=3 80 1066 18 EME240GBB12GT August 22, 2011 2 (2) 1.3 2× 488 78 EME300GBB22GV January 4, 2011 1.6 492 78.7 EME350GBB22GT August 22, 2011 B0 C0 1.65 HD 6320 508 600 81.2 1333 EME450GBB22GV
Brazos 2.0: "Ontario", "Zacate" (2012)
Fabrication 40 nm by TSMC
Socket FT1 (BGA-413)
Based on the Bobcat microarchitecture
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
PowerNow!
DirectX 11 integrated graphics
C-series denote Ontario ; and the E-series denotes Zacate
2.50 GT/s UMI (PCIe 1.0 ×4)
Model Released Fab Step. CPU GPU DDR3 TDP Part number Cores (threads) Clock Turbo Cache Model Config Clock Turbo GFLOPS L1 L2 L3 C-70 colspan="2" colspan="6" E1-1200 E1-1500 E2-1800 E2-2000 September 15, 2012 40 nm C0 2 (2) 1.0 1.33 32 KB inst. 32 KB data per core 2× 512KB rowspan=6 HD 7290 80:8:4 276 400 44.1 1066 9 CMC70AFPB22GV June 6, 2012 C0 1.4 rowspan=4 HD 7310 500 rowspan=2 80 1066 18 EM1200GBB22GV January 7, 2013 1.48 529 84.6 June 6, 2012 1.7 HD 7340 523 680 83.6 1333 EM1800GBB22GV January 7, 2013 1.75 538 700 86
Brazos-T: "Hondo" (2012)
Fabrication 40 nm by TSMC
Socket FT1 (BGA-413)
Based on the Bobcat microarchitecture
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
Found in tablet computers
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
PowerNow!
DirectX 11 integrated graphics
2.50 GT/s UMI (PCIe 1.0 ×4)
Model Released Fab Step. CPU GPU DDR3 Memory support TDP (W) Part number Cores (threads) Clock (GHz) Cache Model Config Clock (MHz) GFLOPS L1 L2 Z-60 October 9, 2012 40 nm C0 2 (2) 1.0 32KB inst. 32KB data per core 2× 512 KB HD 6250 80:8:4 276 44.1 1066 4.5 XMZ60AFVB22GV
"Kabini", "Temash" (2013)
Fabrication 28 nm by TSMC
Socket FT3 (BGA)
2 to 4 CPU Cores (Jaguar (microarchitecture))
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
Turbo Dock Technology, C6 and CC6 low power states
GPU based on Graphics Core Next (GCN)
AMD Eyefinity multi-monitor for up to two displays
Temash, Elite Mobility APU
Model Released Fab Step. CPU GPU DDR3L TDP Part number Cores (threads) Clock Turbo Cache Model Config Clock Turbo L1 L2 A4-1200 A4-1250 A4-1350 A6-1450 May 23, 2013 28 nm KB-A1 2 (2) 1.0 rowspan=3 32 KB inst. 32 KB data per core 1 HD 8180 128:8:4 2 CU 225 rowspan=3 1066 4 AT1200IFJ23HM HD 8210 300 1333 8 AT1250IDJ23HM 4 (4) 2 1066 AT1350IDJ44HM 1.4 HD 8250 400 AT1450IDJ44HM
Kabini, Mainstream APU
Model Released Fab Step. CPU GPU DDR3L TDP Part number Cores (threads) Clock Cache Model Config Clock L1 L2 L3 E1-2100 E1-2200 E1-2500 E2-3000 E2-3800 A4-5000 A4-5100 A6-5200 A4 Pro-3340B May 2013 28 nm KB-A1 2 (2) 1.0 32KB inst. 32KB data per core 1 rowspan=9 HD 8210 128:8:4 2 CU 300 1333 9 EM2100ICJ23HM Feb 2014 1.05 EM2200ICJ23HM May 2013 1.4 HD 8240 400 15 EM2500IBJ23HM 1.65 HD 8280 450 1600 EM3000IBJ23HM Feb 2014 4 1.3 2 EM3800IBJ44HM May 2013 1.5 HD 8330 497 AM5000IBJ44HM Feb 2014 1.55 AM5100IBJ44HM May 2013 2.0 HD 8400 600 25 AM5200IAJ44HM Nov 2014 2.2 HD 8240 400 AM334BIAJ44HM
"Beema", "Mullins" (2014)
Fabrication 28 nm by GlobalFoundries
Socket FT3b (BGA)
CPU: 2 to 4 (Puma cores)
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
GPU based on Graphics Core Next (GCN)
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
Intelligent Turbo Boost
Platform Security Processor, with an integrated ARM Cortex-A5 for TrustZone execution
Mullins, Tablet/2-in-1 APU
Model Released Fab Step. CPU GPU DDR3L TDP Part number Cores (threads) Clock Turbo Cache Model Config Clock Turbo L1 L2 L3 E1 Micro-6200T A4 Micro-6400T A10 Micro-6700T Q2 2014 28 nm ML-A1 2 (2) 1.0 1.4 32 KB inst. 32 KB data per core 1 rowspan=3 R2 128:8:4 2 CU 300 600 1066 3.95 EM620TIWJ23JB 4 (4) 1.6 2 R3 350 686 1333 4.5 AM640TIVJ44JB 1.2 2.2 R6 500 AM670TIVJ44JB
Beema, Notebook APU
Model Released Fab Step. CPU GPU DDR3 Memory support TDP (W) Part number Cores (threads) [FPUs] Clock (GHz) Turbo (GHz) Cache Model Config Clock (MHz) Turbo (MHz) L1 L2 (MB) L3 E1-6010 E1-6015 E2-6110 A4-6210 A4-6250J A6-6310 A8-6410 Q2 2014 28 nm ML-A1 2 (2) 1.35 rowspan=5 32 KB inst. 32 KB data per core 1 rowspan=7 R2 128:8:4 2 CU 300 600 (L)1333 10 EM6010IUJ23JB Q2 2015 1.4 Q2 2014 4 (4) 1.5 2 (L)1600 15 EM6110ITJ44JB 1.8 R3 350 686 AM6210ITJ44JB 2.0 25 1.8 2.4 R4 300 800 (L)1866 15 AM6310ITJ44JB 2.0 R5 AM6410ITJ44JB
"Carrizo-L" (2015)
Fabrication 28 nm by GlobalFoundries
Socket FT3b (BGA), FP4 (μBGA)
CPU: 2 to 4 (Puma+ cores)
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
GPU based on Graphics Core Next (GCN)
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
Intelligent Turbo Boost
Platform Security Processor, with an integrated ARM Cortex-A5 for TrustZone execution
All models except A8-7410 available in both laptop and all-in-one desktop versions
Model Released Fab Step. CPU GPU DDR3 Memory support TDP Part number Cores (threads) [FPUs] Clock Turbo Cache Model Config Clock Turbo L1 L2 E1-7010 E2-7110 A4-7210 A6-7310 A8-7410 A4 PRO-3350B May 2015 28 nm ML-A1 2 1.5 rowspan=2 32 KB inst. 32 KB data per core 1 R2 128:8:4 2 CU 400 (L)1333 10 EM7010IUJ23JB EM7010JCY23JB EM7010JCY23JBD 4 1.8 2 R2 600 (L)1600 12–25 EM7110ITJ44JB EM7110JBY44JB EM7110JBY44JBD 2.2 R3 686 AM7210ITJ44JB AM7210JBY44JBD 2.0 2.4 R4 800 (L)1866 AM7310ITJ44JB AM7310JBY44JB AM7310JBY44JBD 2.2 2.5 R5 847 15 AM7410JBY44JB May 2016 2.0 2.4 R4 800 1600 AM335BITJ44JB
"Stoney Ridge" (2016)
Fabrication 28 nm by GlobalFoundries
Socket FP4 / FT4
2 "Excavator+" x86 CPU cores
L1 Cache: 32 KB Data per core and 96 KB Instructions per module
Single-channel DDR4 memory controller
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
GPU based on Graphics Core Next 3rd Generation with VP9 decoding
Model number Released Fab CPU GPU DDR4 TDP Part number Modules/[FPUs] Clock Turbo Cache Model Config Clock GFLOPS L1 L2 E2-9000e E2-9000 E2-9010 A4-9120 A4-9125 A4-9120C A6-9200e A6-9200 A6-9210 A6-9220 A6-9225 A6-9220C A9-9400 A9-9410 A9-9420 A9-9425 A9-9430 colspan="2" colspan="4" Pro A4-4350B Pro A4-5350B Pro A6-7350B Pro A6-8350B November 2016 28 nm [1]2 1.5 2.0 96 KB inst. per module 32 KB data per core 1 R2 128:8:4 2 CU 600 153.6 1866 6 EM900EANN23AC June 2016 1.8 2.2 10 EM9000AKN23AC 2.0 2.2 10–15 EM9010AVY23AC Q2 2017 2.2 2.5 R3 655 167.6 2133 10–15 AM9120AYN23AC Q2 2018 2.3 2.6 686 175.6 AM9125AYN23AC January 6, 2019 1.6 2.4 R4 192:12:8 3 CU 600 230.4 1866 6 AM912CANN23AC November 2016 1.8 2.7 2133 AM920EANN23AC 2.0 2.8 10 AM9200AKN23AC June 2016 2.4 2.8 10–15 AM9210AVY23AC Q2 2017 2.5 2.9 655 251.5 10–15 AM9220AYN23AC Q2 2018 2.6 3.0 686 263.4 AM9225AYN23AC January 6, 2019 1.8 2.7 R5 720 276.4 1866 6 AM922CANN23AC November 2016 2.4 3.2 800 307.2 2133 10 AM9400AKN23AC June 2016 2.9 3.5 10–25 AM9410AFY23AC Q2 2017 3.0 3.6 847 325.2 AM9420AYN23AC Q2 2018 3.1 3.7 900 345.6 AM9425AYN23AC Q2 2017 3.2 3.5 847 325.2 2400 25 AD9430AJN23AC Q1 2018 2.5 2.9 655 251.5 2133 15 Q1 2020 3.0 3.6 847 325.2 Q1 2018 Q1 2020 3.1 3.7 900 345.6
"Dalí" (2020)
Fabrication 14 nm by GlobalFoundries
Socket FP5
Two Zen CPU cores
Over 30% die size reduction over predecessor (Raven Ridge)
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Dual-channel RAM
"Pollock" (2020)
Fabrication 14 nm by GlobalFoundries
Socket FT5
Two Zen CPU cores
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Single-channel RAM
"Mendocino" (2022)
Main article: Ryzen
Embedded APUs
G-Series
Brazos: "Ontario" and "Zacate" (2011)
Fabrication 40 nm
Socket FT1 (BGA-413)
CPU microarchitecture: Bobcat
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
GPU microarchitecture: TeraScale 2 (VLIW5) "Evergreen"
Memory support: single-channel, support up to two DIMMs of DDR3-1333 or DDR3L-1066
5 GT/s UMI
Model Released Fab Step. CPU GPU DDR3 TDP Part number Cores (threads) Clock Cache Model Config Clock Processing power (GFLOPS) L1 L2 G-Series T24L G-Series T30L G-Series T48L colspan="7" G-Series T16R G-Series T40R G-Series T40E G-Series T40N G-Series T40R G-Series T44R G-Series T48E G-Series T48N G-Series T52R G-Series T56E G-Series T56N March 1, 2011 May 23, 2011 40 nm B0 1 (1) 0.8 1.0 32 KB inst. 32 KB data per core 512 KB rowspan=3 colspan=4 1066 5 GET24LFPB12GTE GET24LFQB12GVE March 1, 2011 May 23, 2011 1.4 18 GET30LGBB12GTE GET30LGBB12GVE March 1, 2011 May 23, 2011 2 (2) 2 × 512 KB GET48LGBB22GTE GET48LGBB22GVE June 25, 2012 B0 1 (1) 0.615 512 KB HD 6250 80:8:4 276 44.1 (L)1066 4.5 GET16RFWB12GVE May 23, 2011 1.0 280 44.8 1066 5.5 GET40RFQB12GVE 2 (2) 2 × 512 KB 6.4 GET40EFQB22GVE January 19, 2011 May 23, 2011 HD 6250 HD 6290 9 GET40NFPB22GTE GET40NFPB22GVE May 23, 2011 1 (1) 512 KB HD 6250 5.5 GET40RFSB12GVE January 19, 2011 May 23, 2011 1.2 9 GET44RFPB12GTE GET44RFPB12GVE June 25, 2012 2 (2) 1.4 2 × 512 KB 18 GET48EGBB22GVE January 19, 2011 May 23, 2011 HD 6310 500 520 80 83.2 GET48NGBB22GTE GET48NGBB22GVE January 19, 2011 May 23, 2011 1 (1) 1.5 512 KB 500 80 1066 1333 GET52RGBB12GTE GET52RGBB12GVE June 25, 2012 2 (2) 1.65 2 × 512 KB HD 6250 275 44 1333 GET56EGBB22GVE January 19, 2011 May 23, 2011 1.6 1.65 HD 6310 HD 6320 500 80 1066 1333 GET56NGBB22GTE GET56NGBB22GVE
"Kabini" (2013, [[System on a chip|SoC]])
Fabrication 28 nm
Socket FT3 (769-BGA)
CPU microarchitecture: Jaguar
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support. No support for FMA (Fused Multiply-Accumulate). Trusted Platform Module (TPM) 1.2 support
GPU microarchitecture: Graphics Core Next (GCN) with Unified Video Decoder 3 (H.264, VC-1, MPEG2, etc.)
Single channel DDR3-1600, 1.25 and 1.35 V voltage level support, support for ECC memory
Integrates Controller Hub functional block, HD audio, 2 SATA channels, USB 2.0 and USB 3.0 (except GX-210JA)
Model Released Fab Step. CPU GPU DDR3 TDP Junction temperature (°C) Part number Cores (threads) Clock Cache Model Config Clock Processing power (GFLOPS) L1 L2 GX-210UA GX-210JA GX-209HA GX-210HA GX-217GA GX-411GA GX-415GA GX-416RA GX-420CA 28 nm B0 2 (2) 1.0 32 KB inst. 32 KB data per core 1 colspan=4 1333 8.5 0-90 GE210UIGJ23HM July 30, 2013 HD 8180E 128:8:4 2 CU 225 57.6 1066 6 GE210JIHJ23HM HD 8400E 600 153.6 9 -40-105 GE209HISJ23HM June 1, 2013 HD 8210E 300 76.8 1333 0-90 GE210HICJ23HM 1.65 HD 8280E 450 115.2 1600 15 GE217GIBJ23HM 4 (4) 1.1 2 HD 8210E 300 76.8 1066 -40-105 GE411GIRJ44HM June 1, 2013 1.5 HD 8330E 500 128 1600 0-90 GE415GIBJ44HM 1.6 colspan=4 GE416RIBJ44HM 2.0 HD 8400E 128:8:4 2 CU 600 153.6 25 GE420CIAJ44HM
"Steppe Eagle" (2014, [[System on a chip|SoC]])
Fabrication 28 nm
Socket FT3b (769-BGA)
CPU microarchitecture: Puma
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
Model Released Fab Step. CPU GPU DDR3 TDP Junction temperature (°C) Part number Cores (threads) [FPUs] Clock Cache Model Config Clock Processing power (GFLOPS) L1 L2 GX-210JC GX-212JC GX-216HC GX-222GC GX-412HC GX-424CC June 4, 2014 28 nm ML-A1 2 (2) [1] 1.0 32 KB inst. 32 KB data per core 1 R1E 128:8:4 2 CU 267 68.3 1600 6 -40-105 GE210JIZJ23JB 1.2 R2E 300 76.8 1333 0-90 GE212JIYJ23JB 1.6 R4E 1066 10 -40-105 GE216HHBJ23JB 2.2 R5E 655 167.6 1600 15 0-90 GE222GITJ23JB 4 (4) [2] 1.2 2 R3E 300 76.8 1333 7 GE412HIYJ44JB 2.4 R5E 497 127.2 1866 25 GE424CIXJ44JB
"Crowned Eagle" (2014, [[System on a chip|SoC]])
Fabrication 28 nm
Socket FT3b (769-BGA)
CPU microarchitecture: Puma
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
no GPU
Model Released Fab CPU GPU DDR3 TDP Junction Part number Cores (threads) [FPUs] Clock Cache L1 L2 GX-224PC GX-410VC GX-412TC GX-420MC June 4, 2014 28 nm 2 (2) [1] 2.4 32 KB inst. 32 KB data per core 1 rowspan=4 1866 25 0-90 GE224PIXJ23JB 4 (4) [2] 1.0 2 1066 7 -40-105 GE410VIZJ44JB 1.2 1600 6 0-90 GE412TIYJ44JB 2.0 17.5 GE420MIXJ44JB
LX-Family (2016, [[System on a chip|SoC]])
Fabrication 28 nm
Socket FT3b (769-BGA)
2 Puma x86 cores with 1MB shared L2 cache
L1 Cache: 32 KB Data per core and 32 KB Instructions per core
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
GPU microarchitecture: Graphics Core Next (GCN) (1CU) with support for DirectX 11.2
Single channel 64-bit DDR3 memory with ECC
Integrated Controller Hub supports: PCIe® 2.0 4×1, 2 USB3 + 4 USB2 ports, 2 SATA 2.0/3.0 ports
Model Released Fab Step. CPU GPU DDR3 TDP Part number Cores (threads) [FPUs] Clock Cache Model Config Clock Processing power (GFLOPS) L1 L2 GX-208JL GX-210JL GX-215GL GX-218GL February 23, 2016 28 nm ML-A1 2 0.8 32 KB inst. 32 KB data per core 1 R1E 64:4:1 1 CU 267 34.1 1333 6 GE208JIVJ23JB GX-210HL 2017 1.0 1066 7 GE208HIZJ23JB February 23, 2016 1333 6 GE210JIVJ23JB GX-210KL 2017 4.5 GE210KIVJ23JB February 23, 2016 1.5 497 63.6 1600 15 GE215GITJ23JB 1.8 GE218GITJ23JB
I-Family: "Brown Falcon" (2016, [[System on a chip|SoC]])
Fabrication 28 nm
Socket FP4
2 or 4 Excavator x86 cores with 1MB shared L2 cache
L1 Cache: 32 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
GPU microarchitecture: Graphics Core Next (GCN) (up to 4 CUs) with support for DirectX 12
Dual channel 64-bit DDR4 or DDR3 memory with ECC
4K × 2K H.265 decode capability and multi format encode and decode
Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports
Model Released Fab CPU GPU Memory support TDP Part number Modules/[FPUs] Cores/threads Clock Turbo Cache Model Config Clock Processing power (GFLOPS) L1 L2 GX-217GI GX-420GI February 23, 2016 28 nm [1] 2 1.7 2.0 96 KB inst. per module 32 KB data per core 1 R6E 256:16:4 4 CU 758 388 DDR3/DDR4-1600 15 GE217GAAY23KA 2016 [2] 4 2.0 2.2 2 R6E R7E 256:16:4 4 CU 384:24:4 6 CU 758 626 388 480.7 DDR4-1866 16.1 GE420GAAY43KA
J-Family: "Prairie Falcon" (2016, [[System on a chip|SoC]])
Fabrication 28 nm
Socket FP4
2 "Excavator+" x86 cores with 1MB shared L2 cache
L1 Cache: 32 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
GPU microarchitecture: Radeon R5E Graphics Core Next (GCN) (up to 3 CUs) with support for DirectX 12
Single channel 64-bit DDR4 or DDR3 memory
4K × 2K H.265 decode capability with 10-bit compatibility and multi format encode and decode
Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports
Model Released Fab CPU GPU Memory support TDP Junction temperature (°C) Part number Modules/[FPUs] Cores/threads Clock Turbo Cache Model Config Clock Turbo Processing power (GFLOPS) L1 L2 GX-212JJ GX-215JJ GX-220IJ GX-224IJ 2018 28 nm [1] 2 1.2 1.6 96 KB inst. per module 32 KB data per core 1 R1E 64:4:1 1 CU 600 rowspan=4 76.8 DDR3-1333 DDR4-1600 6– 0-90 GE212JAWY23AC 2017 1.5 2.0 R2E 128:8:2 2 CU 153.6 DDR3-1600 DDR4-1866 GE215JAWY23AC 2018 2.0 2.2 10– GE220IAVY23AC 2017 2.4 2.8 R4E 192:12:3 3 CU 230.4 DDR3-1866 DDR4-2133 GE224IAVY23AC
R-Series
Comal: "Trinity" (2012)
Fabrication 32 nm
Socket FP2 (BGA-827), FS1r2
CPU microarchitecture: Piledriver
L1 Cache: 16 KB Data per core and 64 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM
GPU microarchitecture: TeraScale 3 (VLIW4) "Northern Islands"
Memory support: dual-channel 1.35 V DDR3L-1600 memory, in addition to regular 1.5 V DDR3
2.5 GT/s UMI
Die size: 246 mm2; Transistors: 1.303 billion
OpenCL 1.1 and OpenGL 4.2 support
Model Released Fab Step. CPU GPU DDR3 TDP Part number Modules/[FPUs] Cores/threads Clock Turbo Cache Model Config Clock Turbo Processing power (GFLOPS) L1 L2 R-252F R-260H R-268D R-272F R-452L R-460H R-460L R-464L May 21, 2012 32 nm B0 [1] 2 1.9 2.4 64 KB inst. per module 16 KB data per core 1 HD 7400G 192:12:4 3 CU 333 417 127.8 1333 17 RE252FSHE23HJE 2.1 2.6 2? HD 7500G 256:16:8 4 CU 327 424 167.4 RE260HSHE24HJE 2.5 3.0 1 HD 7420G 192:12:4 3 CU 470 640 180.4 1600 35 RE268DDEC23HJE 2.7 3.2 HD 7520G 497 686 190.8 RE272FDEC23HJE [2] 4 1.6 2.4 2 × 2 MB HD 7600G 256:16:8 4 CU 327 424 167.4 19 RE452LSHE44HJE 1.9 2.8 HD 7640G 497 655 254.4 35 RE460HDEC44HJE 2.0 HD 7620G 384:24:8 6 CU 360 497 276.4 1333 25 RE460LSIE44HJE 2.3 3.2 HD 7660G 497 686 381.6 1600 35 RE464LDEC44HJE
"Bald Eagle" (2014)
Fabrication 28 nm
Socket FP3
Up to 4 Steamroller x86 cores
L1 Cache: 16 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM
GPU microarchitecture: Graphics Core Next (GCN) (up to 8 CUs) with support for DirectX 11.1 and OpenGL 4.2
Dual channel DDR3 memory with ECC
Unified Video Decode (UVD) 4.2 and Video Coding Engine (VCE) 2.0
Model Released Fab CPU GPU DDR3 TDP Junction temperature (°C) Part number Modules/[FPUs] Cores/threads Clock Turbo Cache Model Config Clock Turbo Processing power (GFLOPS) L1 L2 RX-219NB RX-225FB RX-425BB RX-427BB RX-427NB May 20, 2014 28 nm [1] 2 2.2 3.0 96 KB inst. per module 16 KB data per core 1 colspan="5" 1600 15- 0-100 RE219NECH23JA R4 192:12:4 3 CU 464 533 178.1 RE225FECH23JA [2] 4 2.5 3.4 4 R6 384:24:8 6 CU 576 654 442.3 1866 30- RE425BDGH44JA 2.7 3.6 R7 512:32:8 8 CU 600 686 614.4 2133 30- RE427BDGH44JA colspan="5" RE427NDGH44JA
"Merlin Falcon" (2015, [[System on a chip|SoC]])
Fabrication 28 nm
Socket FP4
Up to 4 Excavator x86 cores
L1 Cache: 32 KB Data per core and 96 KB Instructions per module
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
GPU microarchitecture: Graphics Core Next (GCN) (up to 8 CUs) with support for DirectX 12
Dual channel 64-bit DDR4 or DDR3 memory with ECC
Unified Video Decode (UVD) 6 (4K H.265 and H.264 decode) and Video Coding Engine (VCE) 3.1 (4K H.264 encode)
Dedicated AMD Secure Processor supports secure boot with AMD Hardware Validated Boot (HVB)
Integrated FCH featuring PCIe 3.0 USB3.0, SATA3, SD, GPIO, SPI, I2S, I2C, UART
Model Released Fab Stepping CPU GPU Memory support TDP Junction temperature (°C) Part number Modules/[FPUs] Cores/threads Clock Turbo Cache Model Config Clock Turbo Processing power (GFLOPS) L1 L2 L3 RX-216TD RX-216GD RX-416GD RX-418GD RX-421BD RX-421ND October 21, 2015 28 nm [1] 2 1.6 3.0 96 KB inst. per module 32 KB data per core 1 rowspan=6 colspan="5" DDR3/DDR4-1600 12- 0-90 RE216TAAY23KA R5 256:?:? 4 CU 0.8 rowspan=4 409.6 RE216GAAY23KA [2] 4 2.4 2 R6 384:?:? 6 CU 0.72 552.9 15 -40-105 RE416GATY43KA October 21, 2015 1.8 3.2 384:?:? 6 CU 0.8 614.4 DDR3-2133 DDR4-2400 12- 0-90 RE418GAAY43KA 2.1 3.4 R7 512:?:? 8 CU 819.2 RE421BAAY43KA colspan="5" RE421NAAY43KA
1000-Series
V1000-Family: "Great Horned Owl" (2018, [[System on a chip|SoC]])
Fabrication 14 nm by GlobalFoundries
Up to 4 Zen cores
Socket FP5
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Dual channel DDR4 memory with ECC
Fifth generation GCN based GPU
R1000-Family: "Banded Kestrel" (2019, [[System on a chip|SoC]])
Fabrication 14 nm by GlobalFoundries
Up to 2 Zen cores
Socket FP5
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Dual channel DDR4 memory with ECC
Fifth generation GCN based GPU
2000-Series
V2000-Family: "Grey Hawk" (2020, [[System on a chip|SoC]])
Fabrication 7 nm by TSMC
Up to 8 Zen 2 cores
Fifth generation GCN based GPU
R2000-Family: "River Hawk" (2022, [[System on a chip|SoC]])
Fabrication 12 nm by GlobalFoundries
Up to 4 Zen+ cores
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
Custom APUs
As of May 1, 2013, AMD opened the doors of their "semi-custom" business unit. Since these chips are custom-made for specific customer needs, they vary widely from both consumer-grade APUs and even the other custom-built ones. Some notable examples of semi-custom chips that have come from this sector include the chips from the PlayStation 4 and Xbox One. So far the size of the integrated GPU in these semi-custom APUs exceed by far the GPU size in the consumer-grade APUs.
References
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(October 26, 2018). "AMD quietly launches new Carrizo APU: A8-7680 processor" .
Cutress, Ian. (October 28, 2018). "Day of the Dead: AMD Releases new Carrizo FM2+ APU, the A8-7680" .
(September 23, 2016). "AMD 7th Gen Bristol Ridge and AM4 Analysis" .
"7th Gen AMD Athlon™ X4 940" ."7th Gen AMD Athlon™ X4 940" ."7th Gen AMD Athlon™ X4 940" ."AMD A6-Series A6-9400 - AD9400AGM23AB / AD9400AGABBOX" ."7th Gen A6-9500E APU" ."7th Gen AMD PRO A6-9500E APU" ."7th Gen A6-9500 APU" ."7th Gen AMD PRO A6-9500 APU" ."7th Gen A6-9550 APU" ."7th Gen A8-9600 APU" ."7th Gen AMD PRO A8-9600 APU" ."7th Gen A10-9700E APU" ."7th Gen AMD PRO A10-9700E APU" ."7th Gen A10-9700 APU" ."7th Gen AMD PRO A10-9700 APU" ."7th Gen A12-9800E APU" .(September 19, 2016). "AMD Final Heavy Equipment X Carrier ZEN Bristol Ridge A12-9800 platform change" . BodNara Korea .
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"Opteron Family" ."AMD Opteron X3216 - OX3216AAY23KA" ."AMD Opteron X3418 - OX3418AAY43KA" ."AMD Opteron X3421 - OX3421AAY43KA" ."AMD lists A8-4557M and A10-4657M mobile APUs" .(March 12, 2013). "AMD intros 35W Richland mobile APUs" .
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