Floating-gate MOSFET

History

The concept of using stored charge to gate transistors for electronic memory, was first separately patented by Jack Morton and Ian Ross in 1955 at Bell Labs. Both proposed to store charge in a ferroelectric on the surface of the semiconductor with the purpose of gating electricity for information storage. The MOSFET was invented at Bell Labs between 1955 and 1960, after Frosch and Derick discovered surface silicon dioxide passivation and used their discovery to create the first planar transistors. In 1961, Vasil Uzunoglu and Phillip Koenig, patented the idea applied to MOS-type transistors, also for solid memory. In 1961, Paul Weimer, from RCA, patented insulated electrodes for solid state devices.{{Cite patent|number=US3258663A|title=Solid state device with gate electrode on thin insulative film|gdate=1966-06-28|invent1=Weimer|inventor1-first=Paul|url=https://patents.google.com/patent/US3258663A/en}} A FGMOS with thick insulation between the electrode and ferroelectric was later made in 1967 by Dawon Kahng and Simon Min Sze at Bell Labs and patented by Kahng.

Until 1974, single floating gates were unable to be erased electronically and were not mass produced for electronic storage. Modern FGMOS used in flash memories are based on Fowler-Nordheim tunnelling EEPROM gates, which was invented by Bernward and patented by Siemens in 1974 and further improved by Israeli-American Eliyahou Harari at Hughes Aircraft Company and George Perlegos and others at Intel. Initial applications of FGMOS was digital semiconductor memory, to store nonvolatile data in EPROM, EEPROM and flash memory.

In 1989, Intel employed the FGMOS as an analog nonvolatile memory element in its electrically trainable artificial neural network (ETANN) chip, demonstrating the potential of using FGMOS devices for applications other than digital memory.

Three research accomplishments laid the groundwork for much of the current FGMOS circuit development:

• Thomsen and Brooke's demonstration and use of electron tunneling in a standard CMOS double-poly process allowed many researchers to investigate FGMOS circuits concepts without requiring access to specialized fabrication processes.
• The νMOS, or neuron-MOS, circuit approach by Shibata and Ohmi provided the initial inspiration and framework to use capacitors for linear computations. These researchers concentrated on the FG circuit properties instead of the device properties, and used either UV light to equalize charge, or simulated FG elements by opening and closing MOSFET switches.
• Carver Mead's adaptive retina gave the first example of using continuously-operating FG programming/erasing techniques, in this case UV light, as the backbone of an adaptive circuit technology.

Structure

An FGMOS can be fabricated by electrically isolating the gate of a standard MOS transistor, so that there are no resistive connections to its gate. A number of secondary gates or inputs are then deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG, since the FG is completely surrounded by highly resistive material. So, in terms of its DC operating point, the FG is a floating node.

For applications where the charge of the FG needs to be modified, a pair of small extra transistors are added to each FGMOS transistor to conduct the injection and tunneling operations. The gates of every transistor are connected together; the tunneling transistor has its source, drain and bulk terminals interconnected to create a capacitive tunneling structure. The injection transistor is connected normally and specific voltages are applied to create hot carriers that are then injected via an electric field into the floating gate.

FGMOS transistor for purely capacitive use can be fabricated on N or P versions. For charge modification applications, the tunneling transistor (and therefore the operating FGMOS) needs to be embedded into a well, hence the technology dictates the type of FGMOS that can be fabricated.

Modeling

Large signal DC

The equations modeling the DC operation of the FGMOS can be derived from the equations that describe the operation of the MOS transistor used to build the FGMOS. If it is possible to determine the voltage at the FG of an FGMOS device, it is then possible to express its drain to source current using standard MOS transistor models. Therefore, to derive a set of equations that model the large signal operation of an FGMOS device, it is necessary to find the relationship between its effective input voltages and the voltage at its FG.

Small signal

An N-input FGMOS device has N−1 more terminals than a MOS transistor, and therefore, N+2 small signal parameters can be defined: N effective input transconductances, an output transconductance and a bulk transconductance. Respectively: : g_{mi}=\frac{C_i}{C_T}g_m\quad\mbox{for}\quad i=[1,N] : g_{dsF}=g_{ds}+\frac{C_{GD}}{C_T}g_m : g_{mbF}=g_{mb}+\frac{C_{GB}}{C_T}g_m where C_T is the total capacitance seen by the floating gate. These equations show two drawbacks of the FGMOS compared with the MOS transistor:

• Reduction of the input transconductance
• Reduction of the output resistance

Simulation

Under normal conditions, a floating node in a circuit represents an error because its initial condition is unknown unless it is somehow fixed. This generates two problems:

1. It is not easy to simulate these circuits
2. An unknown amount of charge might stay trapped at the floating gate during the fabrication process which will result in an unknown initial condition for the FG voltage.

Among the many solutions proposed for the computer simulation, one of the most promising methods is an Initial Transient Analysis (ITA) proposed by Rodriguez-Villegas, where the FGs are set to zero volts or a previously known voltage based on the measurement of the charge trapped in the FG after the fabrication process. A transient analysis is then run with the supply voltages set to their final values, letting the outputs evolve normally. The values of the FGs can then be extracted and used for posterior small-signal simulations, connecting a voltage supply with the initial FG value to the floating gate using a very-high-value inductor.

Applications

The usage and applications of the FGMOS can be broadly classified in two cases. If the charge in the floating gate is not modified during the circuit usage, the operation is capacitively coupled.

In the capacitively coupled regime of operation, the net charge in the floating gate is not modified. Examples of application for this regime are single transistor adders, DACs, multipliers and logic functions, and variable threshold inverters.

Using the FGMOS as a programmable charge element, it is commonly used for non-volatile storage such as flash, EPROM and EEPROM memory. In this context, floating-gate MOSFETs are useful because of their ability to store an electrical charge for extended periods of time without a connection to a power supply. Other applications of the FGMOS are neuronal computational element in neural networks, analog storage element and e-pots.

References

References

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