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EDRAM
Dynamic random-access memory included in a processor chip or package
Dynamic random-access memory included in a processor chip or package
Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalent standalone DRAM chips used as external memory, but the performance advantages of placing eDRAM onto the same chip as the processor outweigh the cost disadvantages in many applications. In performance and size, eDRAM is positioned between level 3 cache and conventional DRAM on the memory bus, and effectively functions as a level 4 cache, though architectural descriptions may not explicitly refer to it in those terms.
Embedding memory on the ASIC or processor allows for much wider buses and higher operation speeds, and due to much higher density of DRAM in comparison to SRAM, larger amounts of memory can be installed on smaller chips if eDRAM is used instead of eSRAM. eDRAM requires additional fab process steps compared with embedded SRAM, which raises cost, but the area savings of eDRAM memory offsets the process cost when a significant amount of memory is used in the design.
eDRAM memories, like all DRAM memories, require periodic refreshing of the memory cells, which adds complexity. However, if the memory refresh controller is embedded along with the eDRAM memory, the remainder of the ASIC can treat the memory like a simple SRAM type, such as in 1T-SRAM.
eDRAM is used in various products, including IBM's POWER7 processor,{{cite web |access-date=2009-08-17 | archive-url = https://web.archive.org/web/20130413082728/http://www.anandtech.com/show/6892/haswell-gt3e-pictured-coming-to-desktops-rsku-notebooks | url-status = dead | archive-date = April 13, 2013 | access-date = 2013-10-07
| Product name | Amount of |
|---|---|
| eDRAM | |
| IBM z15 | 256+ MB |
| IBM's System Controller (SC) SCM, with L4 cache for the z15 | 960 MB |
| Intel Haswell, Iris Pro Graphics 5200 (GT3e) | 128 MB |
| Intel Broadwell, Iris Pro Graphics 6200 (GT3e) | 128 MB |
| Intel Skylake, Iris Graphics 540 and 550 (GT3e) | 64 MB |
| Intel Skylake, Iris Pro Graphics 580 (GT4e) | 64 or 128 MB |
| Intel Coffee Lake, Iris Plus Graphics 655 (GT3e) | 128 MB |
| PlayStation 2 | 4 MB (as a framebuffer) |
| PlayStation Portable | 2 MB (for the Media Engine) |
| 2 MB (for the GPU) | |
| Xbox 360 | 10 MB |
| Wii U | 32 MB |
References
References
- [http://www.eetimes.com/author.asp?doc_id=1323410 Intel's Embedded DRAM: New Era of Cache Memory]
- [https://safari.ethz.ch/digitaltechnik/spring2023/lib/exe/fetch.php?media=onur-ddca-2023-lecture21-memory-organization-afterlecture.pdf ETH Zurich Digital Design & Computer Architecture Lecture 21, slide 98]
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