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DisplayID

VESA standard for metadata

Summary

VESA standard for metadata

DisplayID is a VESA standard for metadata describing display device capabilities to the video source. It is designed to replace E-EDID standard and EDID structure v1.4.

The DisplayID standard was initially released in December 2007. Version 1.1 was released in March 2009 and was followed by version 1.2 released in August 2011. Version 1.3 was released in June 2013 and current version 2.0 was released in September 2017.

DisplayID uses variable-length structures of up to 256 bytes each, which encompass all existing EDID extensions as well as new extensions for 3D displays, embedded displays, Wide Color Gamut and HDR EOTF. DisplayID format includes several blocks which describe logical parts of the display such as video interfaces, display device technology, timing details and manufacturer information. Data blocks are identified with a unique tag. The length of each block can be variable or fixed to a specific number of bytes. Only the base data block is mandatory, while all extension blocks are optional. This variable structure is based on CEA EDID Extension Block Version 3 first defined in CEA-861-B.

The DisplayID standard is freely available and is royalty-free to implement.

DisplayID 2.0 structures

Version 2.0 introduces new generalized information blocks primarily intended for UltraHD High Dynamic Range (HDR) displays, such as LCD computer monitors and LCD/OLED televisions with native support for BT.2100 color space and PQ/HLG transfer functions. It also makes optional predefined CRT/LCD timings from DMT and CEA-861 standards, switching to formula-based structures which follow VESA CVT-RB and GTF.

The base DisplayID 2.0 variable-length structure is the same for all data blocks:

Byte offset		Value		Mandatory		Description
0
1
2
3
4
(N+4)

Each data block starts with mandatory block tag, revision number (0-7), and payload length (0-248) bytes, and has a variable length of up to 251 bytes. The following blocks are currently defined:

Block tag		Mandatory		Name		Notes
0x00–0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x7E
0x81

0x20 Product identification

0x20 Product identification block contains standard vendor and product IDs, serial number, date of manufacture and product name.

Comparing to legacy block 0x00, Microsoft ISA Plug&Play identifier is replaced with IEEE OUI, first used in the network MAC address.

Byte offset		Bit/value		Description/format
0
1
2
3–5
6–7
8–11
12
13
14
15–251

0x21 Display parameters

0x21 Display parameters block contains basic parameters such as viewable area size and pixel count, supported color depth, and factory calibrated RGB color space, white point, luminance, and gamma transfer function.

Comparing to legacy block 0x01, color calibration values have been moved here from block 0x02 and max/min luminance values have been added. Display size can be specified in 1 mm increments in addition to default 0.1 mm.

Byte offset		Bit/value
0	`0x21`	Display parameters block tag
1	Bits 2:0 = `0`	Revision
Bit 7	Image size precision:
2	`29`	Number of payload bytes
3–4		Horizontal image size
5–6		Vertical image size
7–8		Horizontal pixel count
9–10		Vertical pixel count
Bits 2:0	Scan orientation:
Bits 4:3	Max luminance information:
Bit 6	Color-space information:
Bit 7	Audio speakers information:
Bits 7:0	x/u' value, 8-bit LSB
Bits 11:8	x/u' value, 4-bit MSB
Bits 15:12	y/v' value, 4-bit LSB
Bits 23:16	y/v' value, 8-bit MSB
24–25		Max luminance (full coverage), cd/m2
26–27		Max luminance (10% coverage), cd/m2
28–29		Min luminance, cd/m2
Bits 2:0	Color Depth:
Bits 6:4	Display technology:
31		Gamma EOTF (1.00–3.54), stored value = (Gamma × 100) – 100 = (Gamma – 1) × 100 (`255`=unspecified)
Notes: Chromaticity values use 12-bit fractional integer numbers (bit12 × 2−1 + ... + bit0 × 2−12)

0x22 Type VII detailed timings

0x22 Detailed timing block type VII defines CTA-861 compatible timings based on pixel rate. This block is based on type VI block 0x13.

Byte offset		Bit/value		Description/format
0
1
Bit 2
2

Byte offset		Bit/value
Bits 7:0	8-bit LSB
Bits 15:8	8-bit middle bits
Bits 23:16	8-bit MSB
Bits 3:0	Aspect ratio:
Bit 4	Frame scanning type:
Bits 6:5	Stereoscopic 3D:
Bit 7	Preferred timing:
4–5		Horizontal active image pixels
6–7		Horizontal blank pixels
Bits 7:0	8-bit LSB
Bits 14:8	7-bit MSB
Bit 15	Horizontal sync polarity:
10–11		Horizontal sync width
12–13		Vertical active image lines
14–15		Vertical blank lines
Bits 7:0	8-bit LSB
Bits 14:8	7-bit MSB
Bit 15	Vertical sync polarity:
18–19		Vertical Sync Width

0x23 Type VIII enumerated timing code

0x23 Type VIII enumerated timing code block is based on type IV DMT ID block 0x06. It provides one-byte or two-byte video mode codes as defined in VESA Display Monitor Timings standard or Video Information Codes defined by CTA-861 and HDMI.

Byte offset		Bit/value		Description/format
0
1
Bit 3
Bits 7:6
2

0x24 Type IX formula-based timings

0x24 Type IX formula-based timings block is based on type V short timings block 0x11.

Byte offset		Bit/value		Description/format
0
1
2

Byte offset		Bit/value		Description/format	0		colspan=2	Timing options
Bits 2:0	Timing Formula/Algorithm

Bit 3	NTSC Video optimized refresh rate × (1000/1001):

Bits 6:5	Stereoscopic 3D:

1–2
3–4
5

0x25 Dynamic video timing range

0x25 Dynamic video timing range block is based on block 0x9h Video Timing Range Limits; the new version allows more precise definition of pixel rate in 1 kHz steps and adds indication for variable refresh rates.

Byte offset		Bit/value		Description/format	11		colspan=2	Dynamic video timing range Support Flags
0	`0x25`
1	Bits 2:0
2	`9`
3–5
6–8
9
10
Bits 1:0	Maximum vertical refresh rate MSB, Hz (block revision 1)
Bit 7	Seamless dynamic video timing change:

0x26 Display interface features

0x26 Display interface features block describes color depth, dynamic range, and transfer function supported by the display controller. It is based on blocks 0x0F display interface features and 0x02 color characteristics.

Byte offset		Bit/value
0	`0x26`	Display interface features block tag
1	Bits 2:0 = `0`	Revision
2	`9`	Number of payload bytes
Bit 0	6 bpc
Bit 1	8 bpc
Bit 2	10 bpc
Bit 3	12 bpc
Bit 4	14 bpc
Bit 5	16 bpc
`0` = no support
Bit 0	8 bpc
Bit 1	10 bpc
Bit 2	12 bpc
Bit 3	14 bpc
Bit 4	16 bpc
`0` = no support
7	Minimum pixel rate for YCbCr 4:2:0 encoding,
pixel rate = 74.25 MP/s × Stored Value (`0`=supported at all modes)
Bit 5	48 kHz sample rate
Bit 6	44.1 kHz sample rate
Bit 7	32 kHz sample rate
`0` = no support
Bit 0	sRGB (IEC 61966-2-1) Color space and EOTF
Bit 1	ITU-R BT.601 Color space and EOTF
Bit 2	ITU-R BT.709 Color space and ITU-R BT.1886 EOTF
Bit 3	Adobe RGB Color space and EOTF
Bit 4	DCI-P3 (SMPTE RP 431–2) Color space and EOTF
Bit 5	ITU-R BT.2020 Color space and EOTF
Bit 6	ITU-R BT.2020 Color space and SMPTE ST 2084 EOTF
`0` = no support
10	`0`	Color space and EOTF combination 2: reserved
11	0–7	Number of additional color space and EOTF bytes (N)
Bits 3:0	EOTF:
Bits 3:0	Color space:

0x27 Stereo display interface

0x27 Stereo display interface block is based on block 0x10and describes stereoscopic 3D/VR modes (i.e. timings codes and stereo frame formats) supported by the display.

Byte offset		Bit/value		Description/format		colspan=2
(6+N+#M1)		colspan=2	One-byte Timing Code #M1	(7+N+M1)	colspan=2	3D Timings descriptor 2
(6+N+M1+#M2)		colspan=2	One-byte Timing Code #M2
0	`0x27`	Stereo Display Interface block tag
1	Bits 2:0	Revision: `0`, `1`
Bits 7:6	Stereoscopic 3D Timing:
2	(N+2)	Number of payload bytes
3	(N+1)	Number of bytes in Stereo Interface Method block
4		Stereo Interface Method code:
Bits 4:0	Timing Code number (M1, 1-31)
Bits 7:6	Timing Code Type:
Note: 3D Timings descriptors only exist when byte 1 bit 6 = `1`

N, Bytes		Bit/value		Description/format	1		colspan=2	Method code: `0` = Frame/Field Sequential	1		colspan=2	`1` = Side-by-Side	8		colspan=2	`2` = Pixel Interleaved	1		colspan=2	`3` = Dual Interface	2		colspan=2	`4` = Multi-view	1		colspan=2	`5` = Stacked Frame
Bit 0	Stereo Polarity:
Bit 0	View Identify:
Bits 7:0	Interleave pattern – 8x8 bit mask
Bit 0	Interface Left and Right Polarity:
Bits 2:1	Mirroring
	Number of Views
	View Interleaving Method Code
Bit 0	View Identity:

0x28 Tiled display topology

0x28 Tiled display topology block describes displays that consist of multiple physical display panels, each driven by a separate video interface. It is based on block 0x12.

Byte offset		Bit/value
0	`0x28`	Tiled Display Topology block tag
1	Bits 2:0 = `0`	Revision
2	`22`	Number of payload bytes
Bits 2:0	Tile Behavior when the only tile being transmitted:
Bits 4:3	Tile Behavior when N tiles (1 2) are being transmitted:
Bit 6	Tile Bezel Descriptor:
Bit 7	Physical Display Enclosure:
Bits 3:0	Number of Vertical Tiles, 4-bit LSB
Bits 7:4	Number of Horizontal Tiles, 4-bit LSB
Bits 3:0	Vertical Tile Location, 4-bit LSB
Bits 7:4	Horizontal Tile Location, 4-bit LSB
Bits 1:0	Vertical Tile Location, 2-bit MSB
Bits 3:2	Horizontal Tile Location, 2-bit MSB
Bits 5:4	Number of Vertical Tiles, 2-bit MSB
Bits 7:6	Number of Horizontal Tiles, 2-bit MSB
Bits 7:0	Horizontal Size, 8-bit LSB
Bits 15:8	Horizontal Size, 8-bit MSB
Bits 23:16	Vertical Size, 8-bit LSB
Bits 31:24	Vertical Size, 8-bit MSB
11		Tile Pixel Multiplier
12		Tile Top Bezel Size
13		Tile Bottom Bezel Size
14		Tile Right Bezel Size
15		Tile Left Bezel Size
Note: Tile Bezel in pixels = (Tile Pixel Multiplier × Tile Bezel Size × 0.1)
16–18		Tiled Display Manufacturer/Vendor ID
IEEE Organizationally Unique Identifier (OUI)
19–20		Tiled Display Product ID LSB/MSB
21–24		Serial number, optional

0x29 Container ID

0x29 Container ID block defines a unique identifier used to associate additional devices that may be present in a multifunctional display.

Byte offset		Bit/value		Description/format	3–18		Bits 128:0		ContainerID
Universally Unique Identifier (UUID)
0	`0x29`
1	Bits 2:0 = `0`
2	`16`

0x7E Vendor-specific data

0x7E Vendor-specific data includes proprietary parameters which are not supported by DisplayID 2.0 structures.

Byte offset		Bit/value		Description/format
0
1
2
3–5
6–224

Byte offset		Bit/value		Description/format
0
1
2–4
5
Bit 7
6
Bits 6:5
7
8

0x81 CTA DisplayID

0x81 CTA DisplayID block provides information on CTA-861 EDID timings.

Byte offset		Bit/value
0	`0x81`	CTA DisplayID block tag
1	Bits 2:0 = `0`	Revision
2	3–248	Number of payload bytes
Bits 4:0	Block 1 Length (L1)
Bits 7:5	Tag code (CTA-861-G)
(L1+2)		CTA Block 2 Tag Code and Block 2 Length

DisplayID 1.3 structures

Version 1.3 information blocks 0x10-0x1F borrow heavily from EDID 1.4 standard, which was designed for previous generation CRT/LCD/DLP/PDP displays.

Byte offset		Value		Mandatory		Description
0
2

The following block types are defined:

Block tag		Name
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x13
0x7F

Note: where indicated, only the difference from similar/superseding structures in Version 2.0 are shown in the sections below.

0x00 Product identification

0x00 Product identification – superseded by 0x20. The difference is:

Byte offset		Bit/value		Description/format
0
3–5

0x01 Display parameters

0x01 Display parameters – superseded by 0x21. The differences are:

Byte offset		Bit/value
0	`0x01`	Display parameters block tag
Bit 0	Deinterlacing
Bit 1	Support_AI in ACP/ISRC packets
Bit 2	Single fixed pixel format only
Bit 3	Single fixed timing only
Bit 4	VESA display power management
Bit 5	Audio input override
Bit 6	Separate audio inputs
Bit 7	Audio support
`0` = no support/no
12		Transfer characteristic gamma EOTF (1.00–3.54), stored value = (Gamma × 100) – 100 = (Gamma – 1) × 100 (`255`=unspecified)
13		Aspect ratio = long axis / short axis (1.00–3.55), stored value = (AR – 1) × 100 (78 for 16:9)
Bits 3:0	Panel native dynamic range, stored value = bpc – 1
Bits 7:4	Display device overall dynamic range, stored value = bpc – 1

0x02 Color characteristics

0x02 Color characteristics – superseded by 0x21 Display parameters.

Byte offset		Bit/value
0	`0x02`	Color characteristics block tag
1	Bits 2:0 = `1`	Revision
Bits 6:3	Transfer characteristic block number
(block `0x0E`)
Bit 7	Color space information:

2	(Np + Nw) × 3 [ + 1 ]	Number of payload bytes; add 1 if Np=0
Bits 3:0	Number of white points (Nw)
Bits 6:4	Number of primaries (Np)
(`0`=Standard color space, additional Identifier byte is added to the block payload)
Bit 7	Color mode:

Bits 7:0	x/u' value, 8-bit LSB,
or
Standard color space identifier code if Np=0:

Bits 11:8	x/u' value, 4-bit MSB
Bits 15:12	y/v' value, 4-bit LSB
Bits 23:16	y/v' value, 8-bit MSB
Notes: Chromaticity values use 12-bit fractional integer numbers (bit12 × 2−1 + ... + bit0 × 2−12)

0x03 Type I detailed timings

0x03 Type I detailed timings – superseded by 0x22 type VII detailed timings. The differences are:

Byte offset		Bit/value		Description/format
0
1

Byte offset		Bit/value		Description/format	0–2		colspan=2	Pixel clock, 10 kHz steps (0.01–167,772.16 MPix/s)	3		colspan=2	Timing options
Bits 3:0	Aspect ratio:

0x04 Type II detailed timings

0x04 Type II detailed timings block provides a compressed structure with less precise pixel coordinates and reduced blank intervals comparing to Type I:

Byte offset		Bit/value		Description/format
0
1
2

Byte offset		Bit/value
Bit 2	Vertical sync polarity:
Bit 3	Horizontal sync polarity:
4		Horizontal active image pixels, 8-bit LSB
Bit 0	Horizontal active image pixels, 1-bit MSB
Bits 3:0	Sync offset (front porch)
Bits 7:4	Sync width
7		Vertical active image lines, 8-bit LSB
9		Vertical blank lines
Bits 3:0	Sync offset (front porch)
Bits 7:4	Sync width
Note: For all pixel dimensions, stored value = (Pixels / 8) – 1

0x05 Type III short timings

0x05 Type III short timings block provides a very short compressed structure which uses formula-based CVT timings.

Byte offset		Bit/value		Description/format
0
1
2

Byte offset		Bit/value
Bits 6:4	Timing formula/algorithm

Bits 3:0	Aspect ratio
1		Horizontal active image pixels
Bit 7	Frame transfer type:

Note: For all pixel dimensions, stored value = (Pixels / 8) – 1

0x06 Type IV short timings

0x06 Type IV short timing (DMT ID code) block uses video mode codes defined in VESA display monitor timings standard, as well as video information codes defined by CTA-861 and HDMI. Superseded by 0x23 enumerated timing.

Byte offset		Bit/value		Description/format
0
1
Bits 7:6
2

0x11 Type V short timings

0x11 Type V short timings block is based on Type III short timings block 0x05, but provides greater pixel precision and only supports CVT-RB. Superseded by 0x24 Type IX formula-based timings.

Byte offset		Bit/value		Description/format
0
1
2

Byte offset		Bit/value		Description/format	0		colspan=2	Timing options
Bits 1:0	Timing formula/algorithm

Bit 4	NTSC Video optimized refresh rate × (1000/1001):

Bits 6:5	Stereoscopic 3D:

Bit 7	Preferred timing:

1–2
3–4
5

0x13 Type VI detailed timing

0x13 Type VI Detailed timing block supports higher precision pixel clock and high-resolution timings. This block is based on Type I block 0x03, but allows greater timings precision using 1 kHz steps instead of 10 kHz. Superseded by 0x22 Type VII Detailed timings.

Byte offset		Bit/value		Description/format
0
1
2

Byte offset		Bit/value
Bits 7:0	8-bit LSB
Bits 15:8	8-bit middle bits
Bits 21:16	6-bit MSB
Bit 22	Aspect and size information:
Bit 23	Preferred timing:
Bits 7:0	Horizontal active image pixels, 8-bit LSB
Bits 14:8	Horizontal active image pixels, 7-bit MSB
Bit 16	Horizontal Sync Polarity:
Bits 7:0	Vertical active image lines, 8-bit LSB
Bits 14:8	Vertical active image lines, 7-bit MSB
Bit 16	Vertical Sync Polarity:
Bits 7:0	Horizontal blank pixels, 8-bit LSB
Bits 15:8	Horizontal offset (front porch), 8-bit LSB
Bits 19:16	Horizontal blank pixels, 4-bit MSB
Bits 23:20	Horizontal offset (front porch), 4-bit MSB
10		Horizontal Sync Width
11		Vertical Blank Lines
12		Vertical Sync offset (front porch)
Bits 3:0	Vertical Sync Width
Bits 6:5	Stereoscopic 3D:
Bit 7	Frame scanning type:
14		Aspect multiplier, aspect ratio = Aspect Multiplier × 3 / 256
Bits 7:0	Vertical image base size, 8-bit LSB
Bits 11:8	Vertical image base size, 4-bit MSB
Bits 15:12	Size Multiplier
Vertical image size = Vertical image base size × Size Multiplier

0x09 Video timing range limits

0x09 Video timing range limits block describes displays capable of variable timings. Superseded by 0x25 Dynamic video timings range.

Byte offset		Bit/value		Description/format	17		colspan=2	Video timing support flags
0	`0x09`
1	Bits 2:0 = `0`
2	`9`
3–5
6–8
9
10
11–12
13
14
15–16
Bit 4	Discrete frequency display
Bit 5	VESA CVT
Bit 6	VESA CVT-RB
Bit 7	Interlaced
`0` = no support/no

0x0C Display device data

0x0C Display device data block provides information about display panel characteristics for embedded applications, such as display technology, panel type, and pixel response times.

Byte offset		Bit/value
0	`0x0C`	Display device data block tag
1	Bits 2:0 = `0`	Revision
2	`13`	Number of payload bytes
Bits 7:0	CRT
Bits 7:4	Display Technology, 4-bit MSB
Bit 2	Backlight can be switched off
Bit 3	Backlight intensity can be controlled
`0` = no support/no
Bits 7:4	Operating Mode code:
5–6		Horizontal pixel count
7–8		Vertical pixel count
9		Aspect Ratio = long axis / short axis (1.00–3.55), stored value = (AR – 1) × 100 (78 for 16:9)
Bits 1:0	Scan direction:
Bits 3:2	Zero pixel location:
Bits 5:4	Rotation capability:
Bits 7:6	Orientation:
11		RGB Sub-pixel Information codes:
12		Horizontal Pixel Pitch, in 0.01 mm steps (0.01% for projection)
13		Vertical Pixel pitch, in 0.01 mm steps (0.01% for projection)
Bits 3:0	Panel native dynamic range, stored value = bpc – 1
Bits 6:0	Pixel response time, in ms (clamped to 0 and 126)
Bit 7	Measurement method:

0x0F Display interface data

Display interface features block – superseded by 0x26 Display Interface Features.

Byte offset		Bit/value
0	`0x0F`	Display Interface Features block tag
1	Bits 2:0 = `0`	Revision
2	`10`	Number of payload bytes
Bits 3:0	Number of links (`1`, `2`, or `4`),
Bits 7:4	Display Interface Type:
Bits 3:0	Interface revision
Bits 7:4	Interface version
Bit 0	6 bpc
Bit 1	8 bpc
Bit 2	10 bpc
Bit 3	12 bpc
Bit 4	14 bpc
Bit 5	16 bpc
`0` = no support
Bit 0	8 bpc
Bit 1	10 bpc
Bit 2	12 bpc
Bit 3	14 bpc
Bit 4	16 bpc
`0` = no support
8	Content Protection support:
Bits 3:0	Standard revision
Bits 7:4	Standard version
Bits 3:0	Spread percentage, in 0.1% increments (range 0 to 1.5%)
Bits 7:6	Spread type supported:
Bit 0	3.3 V
Bit 1	5 V
Bit 2	12 V
Bit 3	2.8 V
`0` = no support
Bit 4	Color mapping:
Bit 0	Shift clock data strobe:
Bit 1	DE polarity:
Bit 2	DE mode :

Additional blocks

Data blocks not described above are:

0x0A Serial number data block provides product serial number as an ASCII string.

0x0B General-purpose ASCII string block provides general purpose text strings that may be required by specific applications.

0xD0 Interface power sequencing block defines display interface signal timings required for entering and exiting sleep mode.

0x0E Transfer characteristics block defines detailed gamma curves according to VESA display transfer characteristic data block (DTCDB) standard, as may be required by byte 1 in 0x02 color characteristics block.

0x10 Stereo display interface block describes stereoscopic 3D/VR modes – superseded by 0x27 Ssereo display interface.

0x12 Tiled display topology data block defines multi-panel displays – superseded by 0x28 tiled display topology.

0x7F Vendor specific block defines proprietary vendor data.

References

(2013-09-23). "VESA Refreshes DisplayID Standard to Support Higher Resolutions and Tiled Displays". vesa.org.
VESA DisplayID Standard, Version 2.0. September 11, 2017
VESA DisplayID Standard, Version 1.3. July 5, 2013

Wikipedia Source

This article was imported from Wikipedia and is available under the Creative Commons Attribution-ShareAlike 4.0 License. Content has been adapted to SurfDoc format. Original contributors can be found on the article history page.

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